EXPLOITING PROGRAMMABLE BIST FOR THE DIAGNOSIS OF EMBEDDED MEMORY CORES D. Appello**, P. Bernardi*, A. Fudoli**, M. Rebaudengo*, M. Sonza Reorda*, V. Tancorre**, M. Violante* * Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy ** ST Microelectronics TPA Mixed Signal Test Solution Group Cornaredo, Italy Abstract 1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a programmable BIST approach and is able to support both testing and diagnosis. Experimental results are provided allowing to evaluate the benefits and limitations of the adopted solution and to compare it with previously proposed ones. The solution takes into account several constraints existing in an industrial environment, such as minimizing the cost of test development, easing the reuse of the available architectures for test and diagnosis of different memory types and minimizing the cost of the external ATE. 1. Introduction Fast innovation in VLSI technologies makes it possible to integrate a complete system into a single chip (System-on-Chip, or SOC). In order to handle the resulting design complexity, reusable cores are being used in many SOC applications. System designers can purchase cores from core vendors and integrate them with their own User-Defined Logic (UDL) to implement SOCs. Core-based SOCs show important advantages: the cost of the end-product is decreased, and thanks to design re-use, the time-to-market is greatly reduced. When speaking of SOCs, the test problem is a major challenge for industries as well as for the research community [1-2]. The main problem lies in the reduced accessibility of cores and UDLs. Traditional approaches [1-3] for testing core-based SOCs completely rely on additional Design for Testability (DfT) structures such as test busses for test transfer from/to the core under test. The access mechanism requires additional logic (such as a wrapper around the core) and wiring (such as a Test Access Mechanism, or TAM) to connect cores to the test 1 This work has been partially supported by the Italian Ministry for University through the Center for Multimedia Radio Communications (CERCOM). source and sink. A crucial point to be solved in SOC testing is the extra cost introduced by the DfT logic, i.e., the area, delay and test application time overheads [4]. Due to the complexity of current SOCs, the adoption of standards allowing reducing the efforts for the integration, debug, and test of the cores they are composed of (as well as of the whole system) is also a major trend [5]. Moreover, the issue of devising efficient methods for the diagnosis of embedded cores is now becoming of increasing importance [6-7] due to the economical impact of faults in SOCs. The adoption of diagnostic analysis is also stimulated by the increased popularity of the Built-In Self-Repair approaches that exploit diagnosis to repair faulty chips using redundant components [8]. In this paper we focus on SRAM embedded memory core test and diagnosis. Since embedded SRAMs are the most widely used cores in SOC applications, extensive research on fault detection in embedded memories has been performed and efficient algorithms have been proposed and implemented [9-10]. BIST provides an effective way to automatically generate test sequences, compressing the outputs and evaluating the goodness of embedded memory cores, and BIST-based solutions are now very popular [11-12]. The typical memory BIST implements a March algorithm [13] composed of a sequence of March elements, each corresponding to a series of read/write operations on the whole memory. Different hardware approaches have been proposed in the literature in order to implement BIST-based March algorithms. The hardwired BIST approach is the most widely used. It consists in adding a custom circuitry to each core, implementing a suitable BIST algorithm [14-15]. The main advantage of this approach is that the test application time is short and the area overhead is relatively small. Hardwired BIST is also a good way to protect the intellectual property contained in the core: the memory core provider needs only to deliver the BIST activation and response commands for testing the core without disclosing its internal design. At the same time, this approach provides very low flexibility: any ITC INTERNATIONAL TEST CONFERENCE Paper 14.1 379 0-7803-8106-8/03 $17.00 Copyright 2003 IEEE