Charge trapping characteristics in high-k gate dielectrics on germanium C. Mahata a, ⁎, M.K. Bera b , P.K. Bose c , C.K. Maiti a a Department of Electronics and ECE, Indian Institute of Technology Kharagpur, India b Department of Electronic Engineering, City University of Hong Kong, Hong Kong c Mechanical Engineering Departments, Jadavpur University, Jadavpur, Kolkata 700032, India abstract article info Available online 17 August 2008 Keywords: High-k gate dielectric Ge Charge trapping The results of a comparative study on the charge trapping/detrapping behavior in thin ZrO 2 and TiO 2 high-k gate dielectrics on p-Ge (100) under stressing in constant current (CCS, 1.02–5.1 C cm - 2 ) and voltage (CVS, - 5 V to - 7 V) at gate injection mode are presented. Stoichiometric thin films of ZrO 2 and TiO 2 have been deposited on p-Ge (100) using organometallic sources at relatively low temperature (b 200 °C) by plasma enhanced chemical vapor deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma discharge at a pressure of 66.67 Pa. The effect of stressing on several important interfacial parameters, like, interface state density, fixed oxide charge, oxide charge centroids, and capture cross-section of traps etc. is reported. © 2008 Elsevier B.V. All rights reserved. 1. Introduction The continued scaling of Si CMOS devices has led to an increased attention to high-k gate dielectrics as replacements for SiO 2 , where eventually the physical thickness (b 10 A) of SiO 2 cannot be scaled further before gate oxide leakage becomes prohibitively large. As per the International Technology Roadmap for Semiconductors (ITRS) published in 2005, by the year 2010, the equivalent oxide thickness of 19 Å and gate leakage currents less than 7 pA/μm, will be required for the MOSFET devices for low standby power applications. High-k dielectrics will be needed for high performance applica- tions, which require very low equivalent oxide thicknesses of less than 1 nm. Much attention has been focused on various high-k dielectrics such as aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ) as possible replacements for SiO 2 , and various research groups have demonstrated high-k dielectrics scaled down to approxi- mately t eq ~10 Å with gate leakage currents significantly reduced compared to conventional SiO 2 -based gates. A major challenge of replacing SiO 2 with a high-k gate dielectric is the degraded channel mobility. Various approaches which enhance electron and hole mobilities, such as the use of strained silicon–germanium (SiGe) on Si, [1] or strained-Si on relaxed buffer SiGe layers [2] are now available. However, bulk Ge has recently received renewed attention as a possible replacement for Si in high-k CMOS devices, because of its higher electron (2.5X) and hole (4X) bulk mobility relative to that of Si allows for the prospect of improved MOSFET channel mobility, while maintaining the potential to continue aggressive device scaling. However, many challenges remain to make high-k on Ge work, such as (i) the presence of traps and fixed charges in the film or at the interfaces, leading to significant flat-band voltage shifts and voltage bias instability; (ii) reliability issues as channel hot carriers and carriers from gate tunneling traverse the gate dielectric resulting in trap generation; and (iii) the degradation of carrier mobility of carriers in the MOSFET channel. In this work, we have made a comparative study on the charge trapping/detrapping behavior in thin ZrO 2 and TiO 2 high-k gate dielectrics on p-Ge (100). Ultra thin layers of high-k dielectrics have been deposited using organometallic sources at a relatively low temperature (b 200 °C) by plasma enhanced chemical vapor deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma discharge. MIS capacitors fabricated using the high-k dielectrics have electrically characterized for reliability studies under both the constant current (CCS at 1.02 C.cm - 2 to 5.10 C.cm - 2 ) and voltage (CVS at - 5 V to - 7 V) stressing in gate injection mode. The effect of stressing on several important interfacial parameters, like, interface state density, fixed oxide charge, and capture cross-section of traps etc. have been studied. 2. Experimental The Ge substrate (100) used was B-doped p-type wafers with a resistivity of 25–29 Ω-cm. We have used dry chemical process for Ge- surface cleaning following reference [3]. Prior to loading in the deposition chamber, samples were cleaned by holding it in highly concentrated HF vapor for 10 to 15 s. High-k TiO 2 and ZrO 2 films (~14 nm) were then deposited using metallorganic compounds titanium tetrakis isopropoxide [Ti(OC 3 H 7 ) 4 ] and zirconium tetratert butoxide [Zr(OC(CH 3 ) 3 ) 4 ] in a microwave (700 W, 2.45 GHz) PECVD system at 500 mTorr for 1 min. No external biasing or heating of the substrate was employed; although the plasma discharge itself raised the substrate temperature to about 150 °C. For electrical measure- ments, metal insulator semiconductor (MIS) capacitors were Thin Solid Films 517 (2008) 163–166 ⁎ Corresponding author. Fax: +91 3222 255303. E-mail address: chandreswar@gmail.com (C. Mahata). 0040-6090/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2008.08.063 Contents lists available at ScienceDirect Thin Solid Films journal homepage: www.elsevier.com/locate/tsf