IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014 2905 Design and Analysis of Copper and Aluminum Interconnects for All-Spin Logic Sou-Chi Chang, Rouhollah Mousavi Iraei, Student Member, IEEE, Sasikanth Manipatruni, Member, IEEE, Dmitri E. Nikonov, Senior Member, IEEE, Ian A. Young, Fellow, IEEE , and Azad Naeemi, Senior Member, IEEE Abstract—In this paper, a conventional spin-valve configura- tion combined with spin-torque-driven switching is used as an energy efficient interconnect structure for all-spin logic. Both Cu and Al interconnect materials are analyzed based on physical models for spin injection, spin transport, and magnetization dynamics. The results indicate proposed metallic interconnects dissipate less energy as compared with all-spin logic interconnects based on the nonlocal spin-valve configuration. Compared with a similar spin interconnect with an Si channel, the spin currents and injection efficiencies are predicted to be higher when a metal like Cu or Al is used due to no Schottky barrier at the interface. Because of the longer spin relaxation length (SRL) in Al as compared with Cu, the delay and energy dissipation are lower when Al is used especially at longer lengths where signal loss becomes important. While metallic spin interconnects are faster and more energy efficient in short lengths because of their smaller resistances and higher spin injection efficiencies, they are outperformed by spin interconnects with Si channels at long lengths because the SRLs in Si can be as long as many micrometers, whereas in metals they are limited to a few hundred nanometers. Index Terms— All-spin logic (ASL), interconnects, nonequilib- rium Greens function (NEGF), spin-transfer torque. I. I NTRODUCTION O VER the past four decades, the ever-increasing com- puting performance of integrated circuits has been the result of the relentless scaling of CMOS field-effect transis- tors (FETs) based on Moore’s law [1]. As we are looking forward to the future technology generations, many beyond- CMOS logic devices have been proposed to augment the conventional Si CMOS technology [2], [3]. Any emerging logic device has to be complemented with compatible fast and energy efficient interconnects. Otherwise, the speed and energy penalities imposed by interconnects may overshadow any intrinsic advantages of a noval switch. Hence, it is of great interest to look at energy efficient interconnects for beyond- CMOS devices. Manuscript received March 21, 2014; revised May 9, 2014; accepted May 23, 2014. Date of publication June 13, 2014; date of current version July 21, 2014. This work was supported by Intel MSR under Contract 2011-IN-2198. The review of this paper was arranged by Editor R. M. Todi. S.-C. Chang, R. M. Iraei, and A. Naeemi are with the School of Elec- trical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail: souchi@gatech.edu; ruhollah.musavi@gmail.com; azad@gatech.edu). S. Manipatruni, D. E. Nikonov, and I. A. Young are with the Components Research, Intel Corporation, Hillsboro, OR 97124 USA (e-mail: sasikanth.manipatruni@intel.com; dmitri.e.nikonov@intel.com; ian.young@intel.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2327057 Fig. 1. (a) Switching components connected by ASL-type interconnects. The blue rectangles are the nanomagnets and the dark gray rectangles are insulating spacers. The arrows show the electrical currents. The dark gray arrows indicate the redundant electrical current paths increasing power dissipation. The light green arrow shows the electrical current with which a considerable fraction of spin current is shunted directly to the ground. (b) Switching components connected by CSV-like interconnects, where the losses resulting from the charge currents in the shunt path of the interconnect and those in the previous ASL switch are eliminated. The yellow rectangle is the tunneling oxide. The initial magnetic unit vectors of the transmitting and receiving nanomagnets are assumed to be [-1, 0, 0] and [1, 0, 0], respectively. Many of the proposed beyond-CMOS devices are based on spintronics [2], [3], i.e., electron spin as a state variable. In par- ticular, a device in a lateral nonlocal spin-valve configuration, also known as all-spin logic (ASL) [4], provides a complete set of Boolean functions with a low operating voltage [5] and has become a promising candidate due to its potential to outperform CMOS logic if proper material improvements are achieved [6]. In ASL, as shown in Fig. 1(a), electrons carrying spin information diffuse through the channel and exchange their angular momentum with the target nanomagnet [7]. The in-built nonreciprocity is achieved by putting the ground location close to the transmitter [8]. Both COPY and INVERT operations can be realized by ASL, meaning that it can be used as a switch or an interconnect. However, this ASL con- figuration is not energy efficient to be used as an interconnect because: 1) a big fraction of spins injected by the transmitter into the channel directly flow into the ground and 2) from the receiver to the ground, there are still redundant current paths increasing power dissipation, which becomes signifi- cant as the interconnect length or number of nanomagnets in the previous stage increases. Therefore, to overcome the problems mentioned previously, the interconnect shown in Fig. 1(b) is used for ASL. In this structure, the spin signal from the previous ASL stage is copied using a conventional 0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.