Int. J. Adv. Sci. Eng. Vol.8 No.4 2425-2430 (2022) 2425 E-ISSN: 2349 5359; P-ISSN: 2454-9967 Avian Frank & Ramesh International Journal of Advanced Science and Engineering www.mahendrapublications.com Design and Analysis of Multiplier Accumulator Circuit for DSP Applications Avian Frank, K. B. Ramesh Department of Electronics and Instrumentation Engineering, RV College of Engineering, Bengaluru, India. 1. INTRODUCTION A Multiplier Accumulator (MAC) unit performs the operations of multiplying two numbers and accumulates the result in a register repeatedly to perform continuous and complex operations. MAC can speed up the process of computation. It has numerous applications in digital signal processing, including filtering, and convolution. MAC also has tremendous applications in audio and video signal processing, Artificial Intelligence (AI), machine learning, military and defense [1]. Since these operations require a cyclic application of multiplication and addition, the speed of execution depends on the overall performance of the MAC unit [2]. Using a MAC unit improves the accuracy and also reduces time delay for computing dot product, matrix multiplication, artificial neural networks, and various mathematical computations. The demand for fast and portable electronic devices has been rising, as they help in accomplishing our day to day tasks. The computation speed of processor is highly dependent on these arithmetic units. The arithmetic unit complexity increases with improvement of the speed and power performance of the processor. Therefore, it is essential to design the unit to reduce the complexity based on the algorithm and number of components used. MAC being the fundamental unit of DSP, it significantly affects the performance of the system. MAC unit comprises of a multiplier and adder. The design parameters of any architecture completely depend on the basic building blocks which are the multiplier and the adder. The enhancement of these building blocks can improve the performance of the overall unit. Along these lines, the enhancement of the multiplier speed and area is a noteworthy test for the framework architects. This test can be effectively overwhelmed by the utilization of various multiplier techniques and appropriate adder circuit. The objective of this paper is to design a MAC unit to perform computation with optimum speed, low power dissipation and chip area. The remainder of this paper is organized as follows. Section 2 explain the basic operation of MAC unit and illustrate an application of MAC. Section 3 explains the design and performance requirements of MAC unit. Section 4 presents various adder circuits. Section 5 presents various multiplier circuits. Rakesh and Sunitha have implemented the novel design of 32-bit MAC unit with 32-bit ABSTRACT: Multipliers and Accumulators are an imperative component of DSP application systems. It plays a vital role in high speed digital signal processing (DSP), image processing multiplier and processing fast Fourier transform (FFT). These computations require large number of multiplication and addition operation which requires dedicated MAC and Arithmetic and Logic Unit (ALU) architectures. Multipliers and adders are the key components of these arithmetic units as it determines the overall performance of the system, i.e. speed, power and area consumed. This paper reviews the components of MAC circuits analyzing and comparing the performance parameters in terms of area, speed and power consumption. Carry Look Ahead adder is the most suitable for low power and for high performance, whereas Wallace tree multiplier can be implemented for chips having larger area and require high speed. Various other multiplier and adder circuits are also reviewed. KEYWORDS: Multipliers and Accumulators, multiplier algorithms, adder circuits, ALU https://doi.org/10.29294/IJASE.8.4.2022.2425-2430 ©2021 Mahendrapublications.com, All rights reserved *Corresponding Author:avianfrank08@gmail.com Received: 05.03.2022 Accepted: 27.04.2022 Published on: 18.05.2022