This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization Taejoong Song, Woojin Rim, Sunghyun Park, Yongho Kim, Giyong Yang, Hoonki Kim, Sanghoon Baek, Jonghoon Jung, Bongjae Kwon, Sungwee Cho, Hyuntaek Jung, Yongjae Choo, and Jaeseung Choi Abstract—Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 μm 2 6T SRAM bitcell is designed for high density (HD), and 0.049 μm 2 for high per- formance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( V MIN ) and assist overheads. The dual-transient wordline scheme is proposed to improve the V MIN by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the V MIN by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications. Index Terms— 10 nm FinFET, dual-transient wordline (DTWL), figure of merit (FOM), high-density (HD), high- performance (HP), low-power, power, performance, and area (PPA) gain, SRAM assist. I. I NTRODUCTION T HE operating voltage (V OP ) of logic transistors has been reduced over technologies to provide low power. Then, to meet the high performance (HP), the threshold voltage (V TH ) has also been reduced accordingly. Fig. 1 illustrates the trend of V OP and V TH over technologies [1]–[16]. However, V TH reduction does not meet the trend of V OP reduction due to the process limitation of gate engineering. Furthermore, since V TH is a dependent variable of the statistical distribution at a nanoscale process, it causes a diminution of the voltage headroom (V OP - V TH ) as shown in Fig. 1. Thus, the logic gate immunity is decreased against the noise and variation by the gradual decrease of V TH [6]–[8]. In order to improve the stability in a low-voltage region, the innovative techniques, such as a postprocessing architecture for error correction or a statistical timing analysis, have been used in [17]. However, it is not easy for an SRAM bitcell to recover from the small voltage headroom, since the transistors of an SRAM bitcell paradoxically support the stability and writability [18]. Manuscript received April 25, 2016; revised June 21, 2016 and August 27, 2016; accepted September 1, 2016. This paper was approved by Guest Editor Atsushi Kawasumi. The authors are with Samsung Electronics Company, Ltd., Hwaseong 445-701, South Korea, (e-mail: tj.song@samsung.com; woojin.rim@samsung.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2016.2609386 Fig. 1. Trend of the operating voltage (V OP ), threshold voltage (V TH ), and the voltage headroom (V OP –V TH ) over technologies [1]–[16]. The voltage headroom is reduced by the saturated V TH , while the SRAM voltage headroom is compensated by V MIN improvement. Recent introduction of assist schemes help to recover the challenges of SRAM voltage-headroom. Fig. 1 describes the minimum operating voltage (V MIN ) of an SRAM that is improved by an assist. The improved headroom is dotted as “V OP - V TH + V MIN improvement,” which is similar to the trend of the V OP trend. It is meaningful that assist helps SRAM voltage-headroom to trace the trend of V OP. Therefore, system-on-chip (SoC) designers can lower the V OP of both SRAM and logic for low-power applications in the nanoscale technology. Meanwhile, an SRAM assist requires the timing or area overhead for the power gain, thus faltering the total gain of power, performance, and area (PPA). This paper explores the various SRAM assist techniques that provide the optimum PPA gain according to the applications in a 10 nm FinFET technology. Then, the dual-transient wordline (DTWL) is proposed to achieve the best PPA gain for a specific bitcell type. The rest of this paper is organized as follows. Section II introduces the 10 nm FinFET technology and the 6T SRAM bitcell. Section III explains the conventional SRAM assist techniques. Section IV illustrates the DTWL technique with the challenge of metal resistance for an assist. Section V shows the SRAM macro with the various assist techniques. Section VI describes the figure-of-merit (FOM) of PPA gain with an SRAM assist. Section VII explains the implementation and measurement of a test chip. 0018-9200 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.