ELEON3LP – Superscalar and low-power enhancements of single issue general purpose processor model Krzysztof Marcinek ⇑ , Witold A. Pleskacz Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warsaw, Poland article info Article history: Available online xxxx Keywords: Superscalar processor Low-power High-performance Power management LEON3 DSM abstract Low power consumption and high-performance are the most important factors in modern embedded System-on-Chip (SoC) designs. Increasing computation complexity and incessant growth of clock fre- quency reveals the necessity for dynamic and smart utilization of the available hardware resources. The paper presents the modified LEON3 processor IP core as an exemplary process of enhancing single issue general purpose processor with superscalar abilities and low-power features. The results of this work can be applied to many existing general purpose processor models to achieve low-power and high-performance systems suitable for modern embedded applications. In comparison with the original LEON3 IP core, the new one may execute up to two instructions per cycle and dynamically manage incor- porated power domains. The Enhanced LEON3 IP core was synthesized for 500 MHz using UMC 90 nm CMOS technology. Performed gate level VCD-based (Value Change Dump) power estimation shows that combining superscalar and low-power techniques allows performing faster program execution with less energy consumption than the original design. Ó 2012 Elsevier B.V. All rights reserved. 1. Introduction Power consumption in SoC Integrated Circuits (ICs) can be di- vided into two categories. The first one is the dynamic power con- sumption caused by performing useful operations and it is proportional to the number of transistor state changes per second. Clock gating [1] is a well-known low-power technique used to re- duce dynamic power consumption in unused system blocks. The easiest way to reduce dynamic power in working functional units is to decrease the clock frequency. However, the clock frequency defines the system performance, so nowadays it cannot be taken into consideration in many applications demanding high speed processing or throughput. Superscalar processing [2] is one of the most exploited approaches to maintain system performance with lower clock frequency, which is essential for reducing dynamic power consumption for low-power applications. The second one, the static power consumption, is the result of the subthreshold leakage current and it is dissipated even if the device has no clock applied. Although in the past days static power could be ignored, in contemporary deep sub-micron (DSM) technologies it plays a sig- nificant role in the total power consumption [3]. Therefore, it is essential to incorporate power management unit [4] utilizing low-power techniques involved in reducing both, dynamic and sta- tic power. A typical superscalar processor performs more than one instruc- tion during the same clock cycle, which means faster program exe- cution and minor demands for operating frequency. By using superscalar and low-power techniques one can choose to work with lower clock frequency and, as a result, lower average power consumption. On the other hand, high frequency and superscalar execution is suitable for more exigent applications. Studies in superscalar processors [5] show that for a significant amount of time particular functional units (FUs) remain idle consuming static power. Power gating [6] is one of the most commonly used low- power techniques in order to avoid this power loss. While cutting off power supply of the unused FU, the source of all parasitic cur- rents is removed. Exploiting superscalar and multiple power do- main system results in spare time when the whole power domain can be shut down reducing power consumption, not only by the dynamic but also by the static power part. The main goal of this work is to present a process of enhancing single issue general purpose processor with superscalar and low- power features on an example of a well-known open-source LEON3 IP core processor [7]. LEON3 is available in the form of a synthesiz- able VHDL model based on SPARC V8 instruction set architecture (ISA). Although this work is focused on a particular processor sys- tem, the design process of superscalar and low-power enhance- ments can be applied to other processor models adjusting them to modern technology requirements. 0141-9331/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.micpro.2012.06.004 ⇑ Corresponding author. E-mail addresses: K.Marcinek@imio.pw.edu.pl (K. Marcinek), W.Pleskacz@ imio.pw.edu.pl (W.A. Pleskacz). Microprocessors and Microsystems xxx (2012) xxx–xxx Contents lists available at SciVerse ScienceDirect Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro Please cite this article in press as: K. Marcinek, W.A. Pleskacz, ELEON3LP – Superscalar and low-power enhancements of single issue general purpose pro- cessor model, Microprocess. Microsyst. (2012), http://dx.doi.org/10.1016/j.micpro.2012.06.004