IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 3, MARCH 2006 185 Co-Optimization of the Metal Gate/High-k Stack to Achieve High-Field Mobility % of SiO Universal Mobility With an EOT nm Zhibo Zhang, Senior Member, IEEE, S. C. Song, Senior Member, IEEE, M. A. Quevedo-Lopez, Kisik Choi, Paul Kirsch, Pat Lysaght, and Byoung Hun Lee, Senior Member, IEEE Abstract—HfO and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are suc- cessfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high- dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO gate stack. Index Terms—Charge carrier mobility, high- gate dielectric, HfO , HfSiON, metal gate, MOSFETs. I. INTRODUCTION T HE conventional poly/SiON gate stack is quickly ap- proaching its scaling limit due to the high gate tunneling leakage current. Hafnium-based dielectrics such as HfO and HfSiON have emerged as the leading candidates to replace SiON in the 45- or 32-nm technology node [1], [2]. However, for aggressively scaled HfO and HfSiON gate dielectrics, mobility degradation has been one of the major limiting factors preventing the introduction of high- gate dielectrics into CMOS technologies [3]–[5]. Recently, we found that the thick- ness of HfO [6] and HfSiON [7] dielectrics plays an important role in determining electron mobility. The metal gate materials also impact carrier mobility [8]. In this paper, we report aggressively scaled HfO and HfSiON gate dielectrics with an equivalent oxide thickness (EOT) approaching 1 nm and with very high electron mobility achieved by co-optimizing the TiN/high- gate stack. The ultrathin TiN metal gate is found to be beneficial for improving mobility while still eliminating gate depletion. Atomic layer deposition (ALD) enables the aggressive scaling of both high- dielectrics and the TiN metal gate. The transient charge trapping in these optimized HfO and HfSiON gate stacks is minimal. The ultrathin HfO and HfSiON films are found to remain near amorphous even after full CMOS processing, Manuscript received October 17; revised January 5, 2006. The review of this letter was arranged by Editor B. Yu. Z. Zhang and M. A. Quevedo-Lopez are with the Texas Instruments, Inc., Dallas, TX 75243 USA (e-mail: z-zhang@ti.com). S. C. Song, K. Choi, and P. Lysaght are with SEMATECH, Austin, TX 78741 USA. P. Kirsch and B. H. Lee are with IBM Corporation, Austin, TX 78741 USA. Digital Object Identifier 10.1109/LED.2006.870245 which we believe plays an important role in improving mo- bility and reducing transient charge trapping, especially for the ultrathin HfO dielectric. For the optimized HfO gate stack, peak mobility cm /V-s and high-field mobility (at mV/cm) % of the SiO universal mo- bility are achieved at an EOT nm; for HfSiON, peak mobility cm /V-s and high-field mobility % of the SiO universal mobility are achieved at an EOT nm. II. EXPERIMENTAL A (100) Si substrate is cleaned with diluted HF followed by ozonated deionized water. Some wafers then receive an additional 700 C, 20-s rapid thermal anneal (RTA) in 30 torr NO ambient to grow nm RT-SiON interface layer. HfO or HfSiO (Hf : Si high- dielectrics (1.6–3.5 nm) are deposited in an Anelva ALD chamber, followed by nitridation with a 700 C, 30-s NH post-deposition anneal. TiN metal gate electrodes (2.3–10 nm) are then deposited in an Anelva ALD chamber using a TiCl -based chemistry, capped with 100 nm amorphous Si ( -Si). A plasma etch process etches the -Si/TiN metal gate stack and stops on the high- dielectric. Other process steps are kept the same as those in a conventional poly/SiO baseline CMOS flow. The dopant activation process is 1000 C, 5-s RTA. The EOT is extracted from the accumulation capacitance- voltage (C–V) curve measured on a cm overlap ca- pacitor. Carrier mobility is calculated from the dc – curve using the NCSU mobility model. III. RESULTS AND DISCUSSION The ALD TiN metal gate thickness shows a noticeable ef- fect on electron mobility. On 3-nm HfO and HfSiON high- dielectrics with an O chemical oxide bottom interface, both peak mobility and high-field mobility are found to increase with decreasing TiN thickness. The mobility improvement is associ- ated with a reduced interface charge trapping density for thinner TiN metal gates [Fig. 1(a)], which could be due to less impurity contaminations from thinner TiN layers [9]. To further scale the EOT of the high- dielectrics and im- prove carrier mobility, we combined ultrathin TiN metal gate (2.3–3.0 nm) with ultrathin high- dielectrics (1.6–2.0 nm), enabled by the excellent film uniformities produced by the ALD processes. Fig. 1(b) shows a high-resolution transmission electron microscopy (TEM) picture of an ultrathin TiN/ultrathin 0741-3106/$20.00 © 2006 IEEE