International Journal of Electrical and Computer Engineering (IJECE) Vol. 12, No. 2, April 2022, pp. 1324~1333 ISSN: 2088-8708, DOI: 10.11591/ijece.v12i2.pp1324-1333  1324 Journal homepage: http://ijece.iaescore.com High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing Fatimazahraa Assad 1 , Mohamed Fettach 1 , Fadwa El Otmani 1 , Abderrahim Tragha 2 1 Department of Physics, Information Processing Laboratory, Hassan II -Casablanca University, Casablanca, Morocco 2 Department of Mathematics, Information Treatment and Modeling Laboratory, Hassan II -Casablanca University, Casablanca, Morocco Article Info ABSTRACT Article history: Received Dec 30, 2020 Revised Aug 6, 2021 Accepted Sep 4, 2021 The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequencies. The design reaches a maximum Throughput of 102.98 Gbps on Virtex 5 and 115.124 Gbps on Virtex 6 in the case of the 6 stages, for 512 bits output length. Although the utilization of the resource increase with the increase of the number of the cores used in each one of the cases. The proposed designs are coded in very high-speed integrated circuits program (VHSIC) hardware description language (VHDL) and implemented in Xilinx Virtex-5 and Virtex-6 A field-programmable gate array (FPGA) devices and compared to existing FPGA implementations. Keywords: FPGA Hardware implementation High performance High throughput Keccak Pipelining SHA-3 This is an open access article under the CC BY-SA license. Corresponding Author: Fatimazahraa Assad Department of Physics, Information Processing Laboratory, Hassan II -Casablanca University Casablanca B.P 7955, Morocco Email: fatimazahraa.assad@gmail.com 1. INTRODUCTION Due to the attacks on the message-digest algorithm 5 (MD5) and secure hash algorithm (SHA-1) hash algorithms [1], [2] the National Institute of Standards and Technology (NIST) has organized a public competition to develop a new hash standard, in which 64 candidates’ algorithms were submitted to NIST for consideration. Among these 51 met the minimum acceptance criteria marking the beginning of the first round of the SHA-3 Competition. The selection of the candidates was based on various evaluation criteria, only 14 were chosen for the second round of the competition. Keccak has been selected as the SHA-3 standard [3]. Keccak is based on a sponge construction which differs from the Merkle–Damgard construction used by MD5, SHA1, and SHA-3 [4]–[6]. With this structure, Keccak is more secure than the existing standards [7]. During and after the NIST's competition several implementations of SHA-3 are presented [8]–[17], [18]. In spite of the availability of software implementations of security algorithms using high powerful central processing unit (CPUs) [19], hardware implementations of these algorithms using high developed platforms such as field- programmable gate arrays (FPGAs) and application specific integrated circuit (ASICs) remains greatly demanded. Optimized hardware implementations of these algorithms in terms of area or throughput are in high demand, depending on whether it concerns slow or fast applications, consequently, these implementations can be optimized either in terms of low area (lightweight implementations) or higher throughput (high-performance