An All-Digital Clock and Data Recovery Circuit for Spread Spectrum Clocking Applications in 65nm CMOS Technology Ching-Che Chung 1 , Duo Sheng 2 , and Yang-Di Lin 1 1 Department of Computer Science and Information Engineering, National Chung Cheng University, No. 168 University Rd., Min-Hsiung, Chia-Yi, Taiwan. 2 Department of Electrical Engineering, Fu Jen Catholic University, No. 510 Chung-Cheng Rd. Hsin-Chung, Taipei, Taiwan. 1 E-mail: wildwolf@cs.ccu.edu.tw Abstract In this paper, an all-digital clock and data recovery (ADCDR) circuit is presented. The proposed ADCDR can recover the data stream sent by a transmitter with a spread spectrum clock generator (SSCG). The proposed adaptive gain control scheme can automatically adjust the phase tracking gain by counting the consecutive identical digits (CID), and the time-to-digital converter (TDC)-based fast phase compensation can quickly compensate for a large phase error. The proposed ADCDR can tolerate input peak- to-peak jitter up to 130ps at 480MHz with the down-spread 10% modulation. In addition, the bit error rate (BER) is less than 10 -12 with 2 31 -1 pseudo-random binary sequence (PRBS). The proposed ADCDR is implemented in a standard performance 65nm CMOS process with standard cells. The active area is 130μm × 100μm, and the power consumption is 1.13mW at 480MHz with the down-spread 10% modulation. Keywords Clock and data recovery (CDR), spread spectrum clock generation (SSCG), phase-locked loop (PLL). 1. Introduction Nowadays, in many high-speed serial link applications, such as USB 3.0, SATA 3.0, PCI-E 3.0, and DisplayPort, the spread spectrum clock generator (SSCG) is adopted in the transmitter part to effectively reduce the electromagnetic interference (EMI) with low hardware cost. The spreading ratio in a SSCG determines the amount of the EMI reduction, and it also influences the jitter performance of the output clock. In addition, the transmitter with a SSCG produces additional jitter to the receiver, and the bit error rate (BER) of the receiver is increased accordingly. Fig. 1 shows the center-spread spread spectrum clock generation with a triangular modulation profile. The spreading ratio is α, the baseline frequency is F center , and the modulation frequency is f m in Fig. 1. The average frequency (baseline frequency) in the center-spread modulation should be equal to the non- spread clock frequency, and the spreading ratio determines the maximum and minimum output frequencies of the SSCG. For example, if F center is 160MHz, and the spreading ratio (α) is 10%, the output clock frequency ranges from 152MHz to 168 MHz. In SATA specifications, the spreading ratio is 5000ppm (0.5%) with a 30 ~ 33 kHz modulation frequency. Thus, the conventional clock and data recovery (CDR) circuit can tolerate the small frequency error produced by the SSCG and still recovers the data correctly. However, if the transmitter can transmit data stream with a larger spreading ratio (>10%), there will be more EMI reduction, as discussed in [1]-[3]. Nevertheless, the frequency error produced by the SSCG will be a design challenge for the CDR circuit design. Therefore, in [4], an adaptive loop filter with a frequency differentiator is proposed to detect the frequency variations during data transmission. However, the CDR circuit [4] requires a non-spread clock as a reference frequency, and thus the frequency error between the transmitter’s and receiver’s frequency synthesizer should be very small to make this circuit operating correctly. In [5], the dual loop CDR circuit is composed of an analog phase- locked loop (PLL) and a digital CDR. The analog PLL with an external oscillator generates high speed multi-phase clock signals for the digital CDR circuit to recover the data stream with up to ±5000ppm (±0.5%) spreading ratio. However, the CDR circuit [5] requires an external reference clock, and thus the cost and power consumption is increased. In addition, the oversampling architecture usually has higher hardware complexity. As a result, a referenceless and non- oversampling type CDR circuit is preferred for spread spectrum clocking applications with a large spreading ratio (>10%). Figure 1: Spread spectrum clock generation. In this paper, a referenceless all-digital clock and data recovery (ADCDR) circuit with an adaptive gain control scheme and time-to-digital converter (TDC)-based fast phase compensation for spread spectrum clocking applications is presented. The proposed ADCDR circuit adjusts the phase tracking gain by counting the consecutive identical digits (CIDs). In addition, the proposed ADCDR This work was supported in part by the National Science Council of Taiwan R.O.C., under Grant NSC100-2221-E-194-051. 978-1-4673-2688-9/12/$31.00 ©2012 IEEE 91 4th Asia Symposium on Quality Electronic Design