A Study of TSV Variation Impact on Power Supply Noise Moongon Jung, Shreepad Panth, and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia, USA Email: {moongon, shreepad.panth, limsk}@gatech.edu Abstract— In this work, we study the through-silicon-via (TSV) RC variation impact on 3D power delivery network (PDN). First, we model TSV RC variation due to process variation. Then, we perform sign-off power supply noise analysis of 3D PDN in GDSII layouts which contain power/ground (P/G) TSV RC variation model. We explore the effect of TSV RC variation range, number of variation sources (P/G TSV count), number of C4 bumps and TSV size on the robustness of PDN under TSV RC variation. Our results show that TSV RC variations cause negligible influence on 3D PDN due to much smaller parasitic values of TSVs compared with that of entire PDN. I. I NTRODUCTION Power delivery is believed to be one of the biggest challenges in 3D stacked ICs. Even though there are many works on 3D power delivery network (PDN), there is no work on TSV RC variation impact on power supply noise in 3D PDN, to the best of our knowledge. Process variation has been critical issues of semiconductor fabrication process, which affects yield, performance, and power consumption. These process variations change the TSV parasitic characteristics, hence affect the quality of PDN. In this work, we explore the impact of TSV RC parasitic variation on the robustness of 3D PDN. Our main contributions are as follows. First, we model TSV RC variation due to process variation. We perform both static (IR-drop) and dynamic noise (voltage droop) analysis on GDSII level 3D IC layouts with TSV RC variation model using existing 2D commercial sign-off level analysis tools. We explore the impact of number of variation sources (P/G TSV count), number of P/G bumps, and TSV RC variation range on the power supply noise. Also we investigate the impact of P/G TSV size and its variation on the 3D PDN quality. II. TSV RC VARIATION Process variations on TSVs are inevitable due to factors such as misalignment, TSV diameter/height and oxide thickness varia- tion, wafer surface cleanliness and roughness. However, extreme misalignment, which causes a systematic variations and increases contact resistance, is highly unlikely in state-of-the-art wafer bonding processes [1]. Thus, TSV RC parasitic variation can be modeled as random effects. In this section, we model TSV RC variation based on TSV dimension variation using analytical models. We ignore TSV inductance since inductive voltage drop by TSV is comparable only for frequencies above several GHz [2], which is not the case for PDN. A. RTSV variation The analytical expression of the dc resistance of TSV is given by RTSV = ρlTSV πr 2 TSV (1) where ρ is the resistivity of conducting material, and rTSV and lTSV represent the radius and height of TSV, respectively. With Cu TSV conductor, the resistivity is 16.8 nΩ·m at 20 ◦ C. Also, we adopt a contact resistivity of 0.45 Ω·µm 2 from measured data based on Cu This material is based upon work supported by the National Science Foundation under Grant No. CCF-0917000, the SRC Interconnect Focus Center (IFC), and Intel Corporation. Fig. 1. TSV resistance vs. TSV diameter and height variation Fig. 2. TSV capacitance vs. TSV diameter and oxide thickness variation direct bonding [3]. Thus, total TSV resistance is sum of TSV dc resistance and contact resistance. We use a TSV with 5 µm diameter, 30 µm height, and 120 nm oxide thickness as a baseline TSV structure. Then, we vary both diameter and height by ±10% of nominal values to model process variation. TSV diameter shows superlinear relationship with TSV resistance while TSV height has linear dependency shown in Figure 1. With fixed TSV height of 30 µm and ±10% of TSV diameter variation, TSV resistance changes from -13.6% to +19.3% of the nominal TSV resistance. B. CTSV variation The nature of the TSV C-V characteristics is similar to the planar MOS capacitor such that accumulation capacitance is the oxide capacitance given as [2] CT SV acc = Cox = 2πϵoxlTSV ln( tox+r TSV r TSV ) (2) As the TSV bias increases, the depletion capacitance acts in series with the oxide capacitance, which is given by CT SV dep = 2πϵsi lTSV ln( tox+r TSV +d dep tox+r TSV ) (3) where tox is the TSV oxide thickness and ddep is the depletion width in silicon substrate. We assume that substrate doping is 2×10 15 /cm 3 . The effective TSV capacitance is the series combination of oxide and depletion capacitances given by 978-1-4577-0502-1/11/$26.00 ©2011 IEEE