Journal of The Electrochemical Society, 147 (11) 4307-4312 (2000) 4307 S0013-4651(00)04-093-3 CCC: $7.00 © The Electrochemical Society, Inc. Chemical mechanical polishing (CMP) is widely used for pla- narization of advanced interconnect and shallow trench isolation structures in integrated circuit manufacture. Of particular concern is within-die variation in the interlevel dielectric or oxide thickness remaining after polish, due to pattern density variations across the die. 1 Recent modeling of CMP has shown that a “planarization length” parameter, corresponding to the length scale over which raised topography (or pattern density) within a die affects local pol- ishing rate, can be used to predict within-die polish performance. 2 As shown by Stine et al., the planarization length PL is the size of an averaging window used to calculate the “effective density” of raised features on the wafer that the CMP process and pad see dur- ing polishing. 3 The local oxide removal rate is then [1] where z is the oxide thickness and K is the blanket polish rate. The effective pattern density  is a function of location x,y on the die, as calculated using the planarization length PL and chip layout infor- mation. Once PL has been determined for a given process, accurate simulation of the within-die thickness profile and nonuniformity re- sulting from CMP can be performed for a given layout. 4 This paper utilizes statistical and semiphysical modeling tech- niques to help understand how planarization length varies across process conditions, as well as within a given wafer. The next section discusses the experimental layout pattern and process conditions used, followed by description of the planarization length extraction procedure. The results of the experiment are then presented, in which the effect on planarization length is characterized as a func- tion of down pressure, table speed, and die position within the wafer. We offer observations on the trade-offs between wafer scale removal rate uniformity, planarization length, and within-die total indicated range. Finally, we summarize our findings and suggest future work. Experimental A total of fifteen 200 mm wafers are prepared with a specialized CMP characterization test pattern, and then subjected to five combi- nations of table speed and down pressure CMP process conditions. The test wafers are fabricated with a blanket polyethylene tetraethyl- orthosilicate (PETEOS) film of 7500 Å, upon which 1 m alu- minum is deposited. The metal film is patterned using the density mask from the MIT CMP characterization mask set. 3 This 12 mm dz dt K x y PL = - (, , ) mask has a 1 mm buffer region around 25 square density blocks, each block being 2 mm in dimension and consisting of an array of patterned lines and spaces sized to generate a desired pattern densi- ty as shown in Fig. 1. The designed (local) pattern densities increase in steps of 4% from a density of 4% in the bottom left corner of the mask to 100% in the top right corner. After metal patterning, a com- bination of PETEOS and high density plasma (HDP) SiO 2 is deposited to give an initial measured oxide thickness before CMP between 2.65 and 2.7 m. The resulting initial oxide step height ranges from 0.92 to 0.94 m across the two test lots processed. The process conditions employed during the CMP process split are summarized in Table I. The experiment is a two factor, two level full factorial with additional center point. The first factor is table speed, with factor levels at high speed (HS) of 54 rotations per minute (rpm), medium speed (MS) of 37 rpm, and low speed (LS) of 20 rpm; the second factor is down pressure with factor levels at HP of 7.74 pounds per square inch (psi), MP of 6.71 psi, and LP of 5.69 psi. In each case, the polishing time is selected so as to remove approxi- mately 1.0 m of the oxide film in the 100% density structure; this ensures that the entire step height is removed from all structures dur- Wafer Scale Variation of Planarization Length in Chemical Mechanical Polishing Charles Oji, Brian Lee,* Dennis Ouma,Taber Smith, Jung Yoon, James Chung, and Duane Boning** ,z Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. However,methods are needed to understand and model both wafer level and die level uniformity in interlevel dielectric (oxide) polishing. This paper examines the variation of die level planarity across the wafer and at different process conditions. Substantial dependency of planarization length, a characteristic length which determines die level planarity, on table speed and down pressure is found, varying from 6.2 to 7.8 mm in the experiments consid- ered here. In addition, a dependence of planarization length on die position within the wafer is found, varying by 0.5 mm across the wafer resulting in a difference of 300 Å total indicated range from one die to the next. Some die are impacted even more strongly resulting in much smaller planarization lengths (near 5.0 mm in some cases) due to wafer edge effects. We conclude that accurate modeling and optimization of within-die variation depends on accurate modeling and measurement of not only wafer scale removal rate variation but also wafer scale planarization length variation. © 2000 The Electrochemical Society. S0013-4651(00)04-093-3. All rights reserved. Manuscript submitted April 26, 2000; revised manuscript received July 20, 2000. ** Electrochemical Society Student Member. ** Electrochemical Society Active Member. * z E-mail: boning@mtl.mit.edu Figure 1. Layout mask used in CMP experiments, where layout density varies from 4% in lower left to 100% in upper right.