552 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998 Simulating the Impact of Pattern-Dependent Poly-CD Variation on Circuit Performance Brian E. Stine, Duane S. Boning, Member, IEEE, James E. Chung, Member, IEEE, Dennis J. Ciplickas, and John K. Kibarian Abstract—In this paper, we present a methodology for simulat- ing the impact of within-die (die-level) polysilicon critical dimen- sion (poly-CD) variation on circuit performance. The methodol- ogy is illustrated on a 0.25 m 64 8 SRAM macrocell layout. For this example, the impact as measured through signal skew is found to be significant and strongly dependent on the input address of the SRAM cell. I. INTRODUCTION I N THE literature, significant research has been focused on understanding the impact of process variation on circuit per- formance [1]–[12], but the majority of this research assumes process variation to be completely random and drawn from ei- ther independent or correlated normal distributions (i.e., Monte Carlo type simulations or design centering methodologies). This approach is adequate when assessing the impact of lot-to- lot or wafer-to-wafer process variation on circuit performance since these types of variation can often be adequately modeled using Gaussian white noise. For pattern-dependent variation, however, this approach is not acceptable because it essentially assumes that the channel length of each transistor on a die can be described by the same underlying random distribution or perhaps with some crude degree of proximity effects included via a correlation structure. Previous studies have empirically observed a correlation between poly-CD variation and circuit performance [13] for small circuits (such as ring-oscillators), but predictive mod- eling of the impact of die-level variation has been difficult. In this paper, we present and illustrate a methodology for de- termining the impact of pattern-dependent polysilicon critical dimension (poly-CD) variation on circuit performance. After describing the methodology in Section II, the methodology is illustrated in Section III via a case study of a 64 8 SRAM Manuscript received December 28, 1997; revised February 24, 1998. This work was supported in part under ARPA Contracts DABT-63-95-C-0088 and DAAH01-96-C-R904, AASERT Grant DAAHA04-95-I-0459, and an Intel Foundation Fellowship. B. E. Stine was with Microsystems Technology Laboratories, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA. He is now with PDF Solutions, Inc., San Jose, CA 95110 USA. D. S. Boning and J. E. Chung are with the Microsystems Technology Laboratories, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail: boning @mtl.mit.edu). D. J. Ciplickas and J. K. Kibarian are with PDF Solutions, Inc., San Jose, CA 95110 USA. Publisher Item Identifier S 0894-6507(98)08363-8. Fig. 1. Flow used to simulate the impact of poly-CD variation on circuit performance in this paper. Fig. 2. Hopkins model used in aerial imaging simulators. Figure and notation derived from [16]. macrocell. Finally, some concluding remarks are offered in Section IV. Poly-CD variation is especially important because it trans- lates directly into MOS transistor channel length variation and resulting variations in the drive current and switching characteristics. Current lithography and etch technology can typically achieve wafer-scale line width uniformity of approx- imately 5–10% (measurements of the same structure within each chip across the wafer). Design rules typically assume that the variation within any one chip will be smaller than this value. However, measurements of supposedly identical structures within the same die reveal variations on the order of 15–20% or more [14], [15]. Clearly, additional physical effects are coming into play at this scale and within-die poly- CD nonuniformity contributes significant variance to the total poly-CD variation budget. 0894–6507/98$10.00  1998 IEEE