A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays Nigel Drego, Anantha Chandrakasan, and Duane Boning Microsystems Technology Laboratories, MIT, Cambridge, MA {ndrego, anantha, boning}@mtl.mit.edu Abstract A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of Devices Under Test (DUTs) has been developed to isolate threshold voltage variation.. Threshold-voltage (V T ) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of V T . Spice simulations show that the structure is at least an order of magnitude more sensitive to V T variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of V T for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm x 2mm DUT array. 1. Introduction Process variation is increasingly becoming a limiting or determining factor in both IC design and manufacture [1]. Nearly all steps within the IC manufacturing process introduce varying degrees of variation in the end device due to limited controllability of the process module. In Deep-Sub-Micron (DSM) CMOS a number of steps can be highlighted as major sources of both random and systematic variation [2]: 1) sub-wavelength lithography, 2) plasma etch, 3) ion implantation and annealing, and 4) chemical-mechanical polishing (CMP) which is increasingly used for STI and poly planarity, and can result in pattern-dependent variation [3]. As gate dimensions continue to decrease, variation in L and V T become increasingly worrisome due to decreasing depth-of-focus of sub-wavelength lithography, line-edge roughness, random discrete dopant fluctuation, stress effects, and oxide thickness ( t ox ) fluctuation. Immersion lithography, extreme ultra-violet (EUV) lithography and improved resist materials may aid in improved control of L. Solutions for improved control of random discrete dopant fluctuation or oxide thickness at the manufacturing level are problematic, meaning these are issues circuit designers and system architects must increasingly be aware of. Recently, there has been an increasing drive to characterize, analyze and better understand the sources of variation as well as their circuit implications. A number of groups, including our own, have studied ring-oscillator frequency to characterize variation at both within-die and die-to-die levels [4][5][6]. While ring-oscillator based techniques enable ease of measurement, isolation of individual parameters for variability study is challenging due to amalgamation of the variation of many transistors into a single parameter (i.e. the frequency of ring operation). The authors of [6] are able to isolate V T by including transistors in pass-gate configuration between each inverter stage of the ring. By using short rings, they are also able to limit the averaging occurring due to parameter lumping. Limiting placement of these rings to scribe-lines, however, does not enable the study of a large number of devices or within-die spatial correlation. The work described in [9] also studies MOSFET threshold voltage mismatch in the sub-threshold domain but is limited to only 400 NMOS “cells” with off-chip current measurements. Furthermore, only the sigma in variation can be calculated and not the actual threshold voltage of each device, making within-die or spatial correlation analysis difficult. In [7], an on-chip ammeter is built to enable collection of transistor I-V curves with digital I/O, enabling measurement of I-V characteristics of a larger number of devices than is typically sustained by common DC probing measurement schemes which require four pads per device. This design allows for complete simulation models to be created but requires tens of supporting transistors for each transistor being measured, resulting in fewer testable devices per unit area. The test structure in [11] also contains a large DUT-array for characterizing device mismatch but requires off-chip measurement and characterization. While the design presented in this work possesses an architecturally similar approach to that in [7], there are fundamental differences: 1) isolation of V T for study, 2) measurements solely within the sub-threshold regime, 3) source and sink DACs and associated logic to eliminate the effect of parasitic leakage currents from DUTs not being accessed, and 4) a much larger number of DUTs. Section 2 describes the high-level architecture and circuits necessary to extract threshold-voltage variation. Section 3 provides the analytic basis used to isolate V T for analysis and characterization, and Section 4 shows Spice simulation results of these circuits. Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED'07) 0-7695-2795-7/07 $20.00 © 2007