1680 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005 A 40-Gb/s CMOS Clocked Comparator With Bandwidth Modulation Technique Yusuke Okaniwa, Hirotaka Tamura, Member, IEEE, Masaya Kibune, Daisuke Yamazaki, Tsz-Shing Cheung, Junji Ogawa, Member, IEEE, Nestoras Tzartzanis, Member, IEEE, William W. Walker, Member, IEEE, and Tadahiro Kuroda, Senior Member, IEEE Abstract—A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11- m standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked ampli- fier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than by laboratory measurements. Index Terms—CMOS integrated circuits, comparators, high-speed integrated circuits. I. INTRODUCTION T O MEET THE ever-increasing demand for bandwidth in telecommunications equipment and servers, component ICs will have to communicate with one another at a very high data rate. To achieve such a rate at a reasonable cost and power consumption, the speed of the CMOS receiver front end must be pushed to its limit. CMOS serializer–deserializer (SERDES) circuits have already reached 10 Gb/s [1]–[11]. To match the capabilities of compound semiconductor and bipolar-based solutions [12]–[20] at lower cost, next-generation CMOS circuits must operate at 40 Gb/s. CMOS 40-Gb/s receivers have been reported [21], [22]. However, these circuits require either a supply voltage or a clock amplitude higher than the standard logic level, adding to the cost and design complexity to achieve the required level of product reliability. We developed a front-end comparator that can receive 40-Gb/s signals at a clock rate of 10 GHz using standard CMOS technology and voltage levels. This paper describes the design and experimental results of the developed comparator. Section II describes the goals in the comparator design. Section III explains the techniques we used to enhance the effective bandwidth of the comparator. Manuscript received September 18, 2004; revised May 2, 2005. This work was supported in part by a Grant in Aid for the 21st Century Center of Excellence for Optical and Electronic Device Technology for Access Network from the Ministry of Education, Culture, Sport, Science, and Technology in Japan. Y. Okaniwa and T. Kuroda are with the Department of Electronics and Electrical Engineering, Keio University, Kanagawa 223-8522, Japan (e-mail: okaniwa@kuro.elec.keio.ac.jp). H. Tamura, M. Kibune, D. Yamazaki, T.-S. Cheung, and J. Ogawa are with the Fujitsu Laboratories Ltd., Kanagawa 223-8522, Kawasaki, Japan. N. Tzartzanis and W. W. Walker are with the Fujitsu Laboratories of America, Inc., Sunnyvale, CA 94085 USA. Digital Object Identifier 10.1109/JSSC.2005.852014 Fig. 1. 40-Gb/s demultiplexer architecture. Section IV shows the circuit of the comparator. Section V describes measurement results of the test chip. II. COMPARATOR DESIGN GOALS The designed comparator is to be used in a 40-Gb/s demul- tiplexer (DEMUX). Specifically, we set the following design goals: • a 10-GHz or higher clock frequency; • avoidance of RF passive devices, such as inductors; • a low-voltage clock swing ( mV - ). The comparator should operate at a clock frequency higher than 10 GHz, otherwise the architecture of the receiver front end becomes too complicated. At a clock rate of 10 GHz, four comparators are needed to capture a 40-Gb/s signal (Fig. 1) at the center of four consecutive unit intervals with 90 clock phase shifts at each comparator. When 2 or higher oversam- pling is used to recover the clock as well as the data, eight or more front-end comparators are needed along with evenly spaced clock phases. If comparators using on-chip spiral inductors for shunt peaking were used in this architecture, the layout would con- sume about several ten times larger area. Transmitting the clock and data over a large distance (e.g., 300 m) to each com- parator without compromising the phase relationships would then present an additional design complication. It is therefore preferable to develop a comparator that can receive 40-Gb/s input signals without inductor peaking. We also prefer to operate with a reduced-swing ( 600 mV - ) clock in order to use high-bandwidth 0018-9200/$20.00 © 2005 IEEE