The effects of post-annealing on the performance of ZnO thin film transistors Seokhwan Bang a , Seungjun Lee a , Joohyun Park a , Soyeon Park a , Youngbin Ko a , Changhwan Choi a , Hojung Chang b , Hyungho Park c , Hyeongtag Jeon a, ⁎ a Division of Materials Science & Engineering, Hanyang University, Seoul 133-791, Republic of Korea b Department of Electronics Engineering, Dankook University, 29 Anseo-dong, Cheonan-shi, Chungnam 330-714, Republic of Korea c Department of Ceramic Engineering, Yonsei University, 134 Shinchon-dong, Seoul, 120-749, Republic of Korea abstract article info Article history: Received 26 April 2010 Received in revised form 18 May 2011 Accepted 18 May 2011 Available online 25 May 2011 Keywords: Atomic layer deposition Zinc oxide Thin film transistor Annealing In this study, we investigated the effects of a post-annealing process on the performance and stability of zinc oxide thin film transistors fabricated by atomic layer deposition. After the post-annealing process in ambient air at 250 °C for 2 h, the value of the saturation mobility increased from 1.2 to 1.8 cm/Vs, the subthreshold swing decreased from 0.53 to 0.34 V/decade, and the I on /I off ratio increased from 3.1 × 10 6 to 1.7×10 7 . The positive bias stability was also enhanced after post-annealing. These results are related to the formation of another phase in which the difference of enthalpy between the semiconductor material and contact metal electrode causes the carrier concentration at the metal/semiconductor interface to increase, leading to decreased contact resistivity. Additionally, internal modification of the semiconductor/dielectric interface and/or improving the semiconductor structure, which is related to a change in the oxidation state of Zn through the incorporation of oxygen and/or hydroxide, can result in improved device performance. © 2011 Elsevier B.V. All rights reserved. 1. Introduction Recently, there has been much interest in the use of oxide semiconductor materials for next generation displays such as smart windows, active matrix organic light emitting diodes (AMOLEDs), and flexible transparent displays [1–3]. Among oxide semiconductor materials, zinc oxide (ZnO)-based semiconductors with wide band gaps (N 3 eV) exhibit several attractive features including non- toxicity, transparency, high mobility, and easy formation even at room temperature. Therefore, they have been recognized as promis- ing solutions for use in high performance backplanes in next generation displays and have been investigated as active layers of TFT. Recently, improvement of TFT performance has been investigat- ed. In order to reduce operation voltage and increase output current, using high-k dielectrics [4,5] and reducing the contact resistance between the channel and the source/drain (S/D) have been proposed [6,7]. Additionally, managing the carrier concentrations of the channel layers by changing process temperature, gas atmosphere, thickness of the channel layer, and using doping materials has been proposed [8–10]. After applying these methods, the fabricated devices must go through an annealing process to optimize their electrical perfor- mance. Post-annealing as the final step is a basic method and is widely used due to its simple process and low cost. However, this post- annealing process cannot only reduce the contact resistance and enhance the crystallinity of the channel layer but also induces changes of the chemical and/or physical characteristics of the channel layer and interfaces between the channel layer and gate dielectric and source/drain metal. These changes may degrade the device perfor- mance according to circumstances. Therefore, it is important to understand the effects of the post-annealing process on each component of the TFTs. We focused on the overall phenomena occurring in the parts of that from ZnO-TFT and the interfaces. In this study, to investigate the effect of the post-annealing process on the chemical/electrical properties of each component of the TFTs, we fabricated ZnO TFTs by ALD because it has many advantages over other deposition techniques including large area capability and good growth control in terms of homogeneity and thickness, even at low temperatures. We measured the chemical and electrical characteris- tics of the TFT components including the metal/active layer interface, active layer, and active layer/dielectric interface before and after the post-annealing process. 2. Experimental details A typical bottom gate type device structure was used for the fabrication of the TFTs. P-type Si substrates (1–10 Ω cm) with a thermally grown 100 nm thick SiO 2 layer were used as the substrates for TFT fabrication. Si and SiO 2 were used as the gate electrode and gate dielectric, respectively. We deposited ZnO films as an active channel layer using a flow-type ALD technique. A 40 nm thick ZnO film was deposited using diethyl zinc [Zn(C 2 H 5 ) 2 ] and de-ionized water as precursor and reactant, respectively, at a process temperature of 100 °C. Thin Solid Films 519 (2011) 8109–8113 ⁎ Corresponding author. E-mail address: hjeon@hanyang.ac.kr (H. Jeon). 0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2011.05.048 Contents lists available at ScienceDirect Thin Solid Films journal homepage: www.elsevier.com/locate/tsf