International Journal of Energy, Information and Communications Vol.6, Issue 3 (2015), pp.39-46 http://dx.doi.org/10.14257/ijeic.2015.6.3.05 ISSN: 2093-9655 IJEIC Copyright ⓒ 2015 SERSC SSTL Based Energy Efficient ISCAS’99 Benchmark Circuit Design on FPGA Amanpreet Kaur 1 , Bishwajeet Pandey 2 , Sunny Singh 3 , Aditi Modgil 4 and Kanika Garg 5 1,2,3,4,5 Chitkara University amanpreet.kaur@chitkara.edu.in 1 , bishwajeet.pandey@chitkara.edu.in 2 , sunny.singh@chitkara.edu.in 3 , aditi.modgil@chitkara.edu.in 4 kanika.garg@chitkara.edu.in 5 Abstract In this work, we are using frequency scaling as power optimization technique. In frequency scaling, frequency is scaled from 1MHz to 1THz, where intermediate values are 10MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz. In this paper we have measured the different power dissipation for different SSTL Logic families with the help of frequency scaling. If we are measuring the clock power, logic power and signals power for different logic families at one frequency then these powers comes out to be the same that concludes that these three powers are same for all the SSTL Logic families for some same frequency .But it had been observed that total power (including clocks, logic, signals, IOs, leakage powers) keeps on changing for different SSTL logic families even at one same frequency. If we are operating on frequency of 1MHz, there will be maximum power dissipation in case of SSTL2_II_DCI and minimum power dissipation in case of SSTL15. Similarly if we are operating on frequency of 10MHz, there will be maximum power dissipation again in case of SSTL2_II_DCI and minimum power dissipation in case of SSTL15. Similarly if we are operating on frequency of 100MHz, 1GHz, 10GHz, 100GHz and there will be maximum power dissipation again in case of SSTL2_II_DCI and minimum power dissipation in case of SSTL15 always. But in case of 1THZ frequency the maximum power dissipation is in case of SSTL2_II logic family and minimum power dissipation in case of SSTL18_I_DCI. Keywords: SSTL, Frequency Scaling, FPGA, VLSI, Device Operating Frequency 1. Introduction A logic family of an integrated circuit is a group of electronic logic gates constructed with compatible logic levels and power supply characteristics within a family. In this paper an approach is made to design the voltage based efficient fire sensor and for that reason we have used four different kinds of Stub Series Terminated Logic (SSTL) IO standards. Voltage based efficient fire sensor have been made by using four different kinds of Stub Series Terminated Logic (SSTL) IO standards [1]. In this paper two standards are being used as a general purpose memory buses which we are (SSTL2) and (SSTL18) [2]. We have also some of the standard that are designed for some specific purpose. JEDEC standard JESD8-15 defines the SSTL18 family and JESD8-9B defines the SSTL2[2]. We have two classes of SSTL2 standards, out of which Class I is being used for unidirectional standards for which a series resistor either of 25 Ω at 2.5V or 20 Ω at 1.8V) needs to be connected to the output of the transmitter [2]. Class II is being used for bidirectional signaling for which we need to connect a resistor of 25 Ω in series to the transceivers’s output. [2].Virtex-6 FPGA is capable of supporting both the standards of signaling either it may be single-ended or differential signaling.[2].FSM is widely used in contemporary logic design [3]. ISCAS’99 benchmark circuit is used to test design on