This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON ELECTRON DEVICES 1 Small- and Large-Signal Performance Up To 175 °C of Low-Cost Porous Silicon Substrate for RF Applications Martin Rack , Yasmina Belaroussi , Khaled Ben Ali, Gilles Scheen, Babak Kazemi Esfeh , and Jean-Pierre Raskin Abstract — This paper focuses on the comparison of the RF performances of various advanced trap-rich (TR) silicon- on-insulator (SOI) and porous silicon (PSi) substrates. The PSi substrates are produced by electroporisification start- ing either from cheap standard resistivity (10 ·cm) sil- icon (PSi-S) or from the most widespread highly doped milliohm-centimeterSi wafers (PSi-M). Through small-signal RF measurements, it is shown that TR-enhanced high- resistivity silicon and both types of PSi are acceptable for RF applications, showing high effective resistivities and low RF substrate losses. What is more the substrate effective permittivity is decreased in the PSi substrates providing higher coupling isolation at high frequencies. Furthermore, large-signal harmonic distortion measurements reveal very strong linearity for both PSi substrates, with PSi-S achiev- ing 50-dB improvement over the already highly linear TR substrate. Finally, RF characterization was carried out over temperature from 25 °C to 175 °C. While the performances of TR and PSi-M substrate rapidly deteriorate above 120 °C, the cost-effective PSi-S substrate maintains high performance all the way up to 175 °C, allowing it a wider range of potential applications. Index Terms— Effective dielectric permittivity, effective resistivity, harmonic distortion (HD), high temperature, microwave losses, porous silicon (PSi), RF characterization, RF substrate, silicon-on-insulator (SOI) technology, trap-rich (TR) high-resistivity (HR) silicon. I. I NTRODUCTION S ILICON-BASED technology has become the preferred choice for applications in RF circuits due to the rapid progress of silicon process and device technologies. Driven by the market demands for continual innovation and by the increasing data rates of emerging communication standards, selection of the right substrate technology can provide strategic advantages for the cointegration of high-speed digital circuits Manuscript received December 14, 2017; revised February 23, 2018; accepted March 17, 2018. The review of this paper was arranged by Editor M. S. Bakir. (Corresponding author: Martin Rack.) M. Rack, K. B. Ali, G. Scheen, B. K. Esfeh, and J.-P. Raskin are with the Department of Electrical Engineering, Université Catholique de Louvain, 1348 Louvain-la-Neuve, Belgium (e-mail: martin.rack@uclouvain.be). Y. Belaroussi is with the Division of Microelectronics and Nan- otechnology, Center de Développement de Technologies Avancées, Algiers 16303, Algeria. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2018.2818466 alongside analog and RF front-end modules on the same chip. Indeed, the design of mixed-signal integrated circuits contin- ues to be challenged by the substrate itself, as it is responsible for RF losses, for RF noise coupling issues, and for nonlinear signal distortion. Due to the conductive nature of a standard resistivity digital silicon substrate (around 10 ·cm), digital switching noise can easily be injected into, and propagate through, the bulk of the substrate and affected sensitive analog and RF circuitry on the same chip, thereby seriously limiting the integration capabilities for RF systems on chip (SoCs). By engineering and optimizing the underlying handle substrate itself, these limitations can be pushed back, enabling new integration levels to be reached [1]. In this context, substrates with high effective resistivities and low effective permittivities are preferred for RF applications as they offer higher quality passives, reduced RF losses, decreased crosstalk levels, and improved linearity (i.e., reduced signal distortion). Although high-resistivity (HR) low-doped silicon-on- insulator (SOI) substrates seem like ideal candidates for the integration of RF front-end modules, it is well known that they suffer from parasitic surface conduction (PSC) effects beneath the buried oxide (BOX) layer, which degrade the effective resistivity of the substrate sensed by coplanar circuits and tech- nology [2]. Indeed, it has been previously shown that the effec- tive resistivity of HR-SOI substrates for integrated coplanar waveguide (CPW) lines is lower than the substrate’s nominal resistivity by more than 1 order of magnitude [2]–[4]. Due to the presence of fixed charges (usually positive [5]) in the BOX layer, the carrier densities at the Si/SiO 2 interface are modified, and a highly conductive region (accumulation or inversion) is induced at this surface. Such PSC effects reduce the effective resistivity sensed by coplanar technology, and the high-valued nominal resistivity characteristics of the HR bulk volume are eclipsed by these highly conductive regions induced at the BOX interface. They are responsible for the increases both in the RF substrate losses and in the crosstalk noise levels [6]. Furthermore, the electrical properties of an HR substrate are highly voltage dependent and possess consequently poor linearity. In fact, it has been shown in [7] and [8] that the generated harmonics coming from the passive compo- nents can have higher power levels than those from the RF switches or other active devices fabricated on HR-SOI. The electrical performances of HR are strongly dependent on 0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.