A Review on Implementation of UART using Different Techniques Ashwini D. Dhanadravye , Samrat S. Thorat Department of Electronics & Telecommunication, Government College of Engineering, Amravati, India Abstract- Universal Asynchronous Receiver Transmitter (UART) is widely used serial data transmission protocol to support full duplex communication. UART can be implemented in a several ways according to the application required by the designer. Some of the UART contain FIFOs for the receiver or transmitter as data buffer; some of them have the 9 data bits mode and so on. This paper presents the review on such different techniques which were using with UART for reliable data transmission. The design of UART mainly consists of three kernel modules which are receiver module, transmitter module and baud rate generator playing an important role in serial communication between the UART and host CPU. Keywords- Asynchronous serial communication, Baud rate generator, Receiver, Transmitter, UART, VHDL. 1. INTRODUCTION In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback and emerges as effective method in many applications for long distance communication as it reduces the signal distortion because of its simple structure. Universal Asynchronous Receiver Transmitter (UART) is a kind of serial communication protocol. The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely-used device for data communication in the field of telecommunication. It has many advantages such as simple resources, reliable performance, strong anti- jamming capability, easy to operate and realize and so on The UART is a large scale integrated circuit which contains all the software programming necessary to fully control the serial port of a PC (Personnel computer). UART performs parallel-to-serial conversion on data character received from the host processor into serial data stream, and serial-to-parallel conversion on serial data bits received from serial device to the host processor. It also adds the start and stop bit to the data for synchronization. In addition to the basic job of converting data from parallel to serial for transmission and from serial to parallel on reception, a UART will usually provide additional circuits for signals that can be used to indicate the state of the transmission media and to regulate the flow of data in the event that the remote device is not prepared to accept more data. 2. THE UART MODULES The UART serial communication module is divided into three sub-modules: the baud rate generator, receiver module and transmitter module Therefore, the implementation of the UART communication module is actually the realization of the three sub-modules [5].The baud rate generator is actually a frequency divider that can be calculated according to system clock frequency and the desired baud rate. The function of baud rate generator is to produce a local clock signal which is much higher than the baud rate to control the UART receive and transmit. The receiver performs serial-to-parallel conversion on the asynchronous data frame received from the serial data input. The transmitter module converts the bytes into serial bits according to the basic frame format received from the CPU. In order to synchronize the asynchronous serial data and to insure the data integrity, start, parity and stop bits are added to the serial data. Fig. 1 UART Module A UART has standard data frame format which consists of a start bit ‘0’, 5-8 bits data, optional parity bit and stop bit ‘1’. Fig. 2 shows the data frame format of a UART. While in idle state, serial data line will be in logic ‘1’ state. A start bit ‘0’ at the beginning of the data frame will cause a falling edge on the serial data line. This marks the detection of a data character. The idea of start bit and stop bit in UART is to achieve data synchronization. An optional parity bit can be in odd parity or even parity. Odd parity means that sum of all bits gives an odd number, while even parity means sum of all bits gives an even number. The serial data frame is shifted out with the least significant bit (LSB) first. Ashwini D. Dhanadravye et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (1) , 2014, 394-396 www.ijcsit.com 394