Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Numerical simulation of self-alignment of chip resistor components for dierent silver content during reow soldering A.M. Najib a,c , M.Z. Abdullah b, , A.A. Saad a , Z. Samsudin d , F. Che Ani d a School of Mechanical Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Penang, Malaysia b School of Aerospace Engineering, Universiti Sains Malaysia, Engineering Campus, 14300 Nibong Tebal, Penang, Malaysia c Advance Mechatronic Laboratory, Faculty of Manufacturing Engineering, Universiti Teknikal Malaysia Melaka, Durian Tunggal, Hang Tuah Jaya 76100, Melaka, Malaysia d Jabil Circuit Sdn. Bhd., Bayan Lepas Industrial Park, 11900, Penang, Malaysia ARTICLE INFO Keywords: Self-alignment SAC solder Surface tension Micro assembly ABSTRACT Three-dimensional simulation and experimental investigation of self-alignment phenomena during the reow soldering process were presented. The multiphase ow model was developed using ANSYS Fluent to investigate the self-alignment eect of laminar melted lead-free solder during the reow phase on board. User-dened function with c-code was integrated into the model, Volume of Fluid (VOF) method was applied to the melt front tracking, and solidication model was used for the phase change solder material. The material used in the study was SAC 105, SAC 305 and SAC 405. The specic heat, latent heat, solidus temperature, liquidus temperature of the lead-free solder and geometrical data for model input was determined experimentally. The model was va- lidated experimentally. The self-alignment capability of dierent lead-free solder was presented. It has been observed that higher silver content solder (SAC 405) have higher self-alignment capability during reow sol- dering compare to SAC 305 and SAC 105. Moreover, all cases show self-alignment in perpendicular to the longer sides of chip resistor travelled more towards the central position. The experimental and simulation results are in good conformity and can be extended for dierent cases. 1. Introduction Recent trends in surface mount technology demanded the need for miniaturization, lower cost, higher density package and higher perfor- mance. Although high lead count ICs have a great interest today [1], high integration of smaller size passive discrete chip component in electronic packaging still important and oer substantial benet for the cost in assembly. At the initial stage of the surface mount assembly process, the solder paste is printed on the copper pad that covered by surface nishes (e.g., ENIG, Imm Ag, and Imm Sn). Then, the automated placement machine deposits the surface mount components (SMCs) into the solder paste. The chip component is deposited with a given extent of positional oset. As the solder is in a liquid state, the self-alignment of passive components occurs. The ability to align during reow soldering process attracted plenty of researchers to study the phenomenon. In this tech- nique, the net force that is mainly governed by surface tension force associated with the melted solder alloy has the intrinsic property of surface tension and tends to bring the moving part into alignment. Some studies include an analytical solution to investigate the self- alignment process in electronic packaging assemblies. For example, Kim et al. [2] reported a dynamic self-alignment model for a Flip-chip assembly. In the study, the solder joint has been considered as a vis- cously damped spring-mass-damper system. The equivalent damping and spring constants represent the equation were calculated. Fennell et al. [3] using the analytical model to analysis the ip chip undergoing rotation in the presence of a viscous underll. Understanding of self- alignment process has been enhanced through a force model by Gao S. and Zhou Y. [4]. They have proposed a semi-analytical self-alignment force model by utilizing surface minimization approach. A complex phase diagram of the restoring torque for misalignment analysis was obtained. A mathematical model has been developed to study the 2- dimensional self-alignment motion of ip-chip assembly by [5]. The study comprises three forces in particular, surface tension force, viscous force and inertial force. The viscous force relates to the force resisting the self-alignment motion mainly by the solder underll, and inertial force was associated with the accelerated mass. An analytical model of lateral capillary forces was developed by Mastrangeli et al. [6] to in- vestigate dynamics of alignment for large displacements. In ip chip assembly with submicron accuracy, Nah et al. [7] make used of surface http://dx.doi.org/10.1016/j.microrel.2017.10.011 Received 24 April 2017; Received in revised form 10 October 2017; Accepted 12 October 2017 Corresponding author. E-mail address: mezul@usm.my (M.Z. Abdullah). Microelectronics Reliability 79 (2017) 69–78 0026-2714/ © 2017 Elsevier Ltd. All rights reserved. MARK