Research Article Reduced-Complexity LDPC Decoding for Next-Generation IoT Networks Muhammad Asif , 1 Wali Ullah Khan , 2 H. M. Rehan Afzal , 3 Jamel Nebhen , 4 Inam Ullah , 5 Ateeq Ur Rehman , 6 and Mohammed K. A. Kaabar 7,8,9 1 College of Electronics and Information Engineering, Shenzhen University, Shenzhen, Guangdong, 518060, China 2 Interdisciplinary Centre for Security, Reliability and Trust (SnT), University of Luxembourg, 1855 Luxembourg City, Luxembourg 3 School of Electrical Engineering and Computing, University of Newcastle, NSW, Australia 4 School of Computer Science and Engineering, Prince Sattam Bin Abdulaziz University, Alkharj 11942, Saudi Arabia 5 College of Internet of Things (IoT) Engineering, Hohai University, Changzhou, China 6 Department of Electrical Engineering, Government College University, Lahore 54000, Pakistan 7 Jabalia Camp, United Nations Relief and Works Agency (UNRWA) Palestinian Refugee Camp, Gaza Strip Jabalya, State of Palestine 8 Gofa Camp, Near Gofa Industrial College and German Adebabay, Nifas Silk-Lafto, 26649 Addis Ababa, Ethiopia 9 Institute of Mathematical Sciences, Faculty of Science, University of Malaya, Kuala Lumpur 50603, Malaysia Correspondence should be addressed to Mohammed K. A. Kaabar; mohammed.kaabar@wsu.edu Received 15 April 2021; Revised 19 May 2021; Accepted 24 August 2021; Published 22 September 2021 Academic Editor: Simone Morosi Copyright © 2021 Muhammad Asif et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Low-density parity-check (LDPC) codes have become the focal choice for next-generation Internet of things (IoT) networks. This correspondence proposes an efficient decoding algorithm, dual min-sum (DMS), to estimate the first two minima from a set of variable nodes for check-node update (CNU) operation of min-sum (MS) LDPC decoder. The proposed architecture entirely eliminates the large-sized multiplexing system of sorting-based architecture which results in a prominent decrement in hardware complexity and critical delay. Specifically, the DMS architecture eliminates a large number of comparators and multiplexors while keeping the critical delay equal to the most delay-efficient tree-based architecture. Based on experimental results, if the number of inputs is equal to 64, the proposed architecture saves 69%, 68%, and 52% area over the sorting-based, the tree-based, and the low-complexity tree-based architectures, respectively. Furthermore, the simulation results show that the proposed approach provides an excellent error-correction performance in terms of bit error rate (BER) and block error rate (BLER) over an additive white Gaussian noise (AWGN) channel. 1. Introduction Internet of things (IoT) will be one of the major trends in next- generation wireless networks for connecting billions of devices to the Internet [1–4]. These communication devices will pro- vide a high data rate with low transmission delay and energy consumption [5–8]. In this regard, low-density parity-check (LDPC) codes [9–15] are one of the most promising candidates in the list of error-control codes and adopted as a primary choice for next-generation IoT networks [16–19]. Compared to other error-correction codes, like Bose- Chaudhuri-Hocquenghem (BCH) codes, Reed Solomon (RS) codes, and turbo codes, LDPC codes have many advantages, e.g., very low error floor, high-speed encoder and decoder, and more varieties in code construction [20–23]. Therefore, LDPC codes have become the focal choice for many commu- nication standards, such as 10-Gigabit Ethernet (802.3an) [24] and Wi-Fi (802.11n/ac/ad) [25–27]. To obtain an optimal performance, LDPC codes are usually decoded with an iterative process between the two Hindawi Wireless Communications and Mobile Computing Volume 2021, Article ID 2029560, 10 pages https://doi.org/10.1155/2021/2029560