Microprocessors and Microsystems 55 (2017) 1–12 Contents lists available at ScienceDirect Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro An efficient trade-off between yield and energy for eDRAM caches under process variations Joonho Kong a,∗ , Young-Ho Gong b a School of Electronics Engineering, Kyungpook National University, Daegu 702-701, South Korea b Department of Computer Science, Korea University, Seoul 136–713, South Korea a r t i c l e i n f o Article history: Received 5 June 2017 Accepted 12 September 2017 Available online 18 September 2017 Keywords: Embedded dynamic random access memory Process variation Refresh Yield Energy-efficiency a b s t r a c t eDRAM cells have been considered as a promising alternative to conventional SRAM cells and already adopted in commercial processors. However, eDRAM cells need to be refreshed periodically, resulting in non-negligible energy and performance overhead. Moreover, under process variations, retention time of eDRAM cells exhibits non-uniform distributions. This phenomenon affects both manufacturing yield and eDRAM refresh burden. In this paper, we first analyze eDRAM module (cache) yield and retention time failure patterns under process variations. Based on our analysis, we disclose most of the failing cache lines have only one faulty cell and propose a cost-efficient technique to save those one-cell failing cache lines. Our technique maintains a one-cell failing line (OFL) buffer which manages the status of the one- cell failing cache lines. By effectively curing one-cell failing lines, our technique significantly improves manufacturing yield by up to 46.1% under the identical refresh intervals. In addition, our technique can be used to loosen refresh intervals with comparable yield. By using the loosened refresh intervals, our technique reduces energy per instruction and improves performance by up to 19.9% and 1.3%, respectively. © 2017 Elsevier B.V. All rights reserved. 1. Introduction A growing demand for memory bandwidth is one of the key challenges in modern high-performance computer architecture de- sign. Data-intensive workloads have emerged as key applications for future computer systems (e.g., big data analytics, cognitive computing, etc.). To effectively reduce data traffic between off-chip main memory and processing cores, contemporary processors of- ten adopt large-scale last-level caches, which eventually increases on-chip data accesses and reduces off-chip traffic. There are sev- eral feasible choices for large-scale on-chip cache memory storage cells. The most common solution is to use SRAM cells for data stor- ages. Traditionally, they are considered as the most common on- chip memory cells thanks to fast access time and high stability. As process technology nodes shrink below 100 nm, however, leak- age power consumption in SRAM cells has significantly increased. It means, particularly for large-scale caches, leakage power con- sumption from SRAM cells would occupy a large portion of system power consumption, making SRAM cells a less attractive solution for large-scale on-chip caches. ∗ Corresponding author. E-mail addresses: joonho.kong@knu.ac.kr (J. Kong), kyh555@korea.ac.kr (Y.-H. Gong). Meanwhile, eDRAM (embedded DRAM) cells [1] have emerged as an attractive solution for data storages of large-scale on-chip caches. An eDRAM cell consists of one access transistor and one capacitor (as in commodity DRAM cells), resulting in much higher cell density and lower leakage power consumption compared to conventional 6T SRAM cells. In fact, several commercial processors already adopted eDRAM cells for their last-level caches (e.g., IBM Power8 [2], Intel Skylake [3], etc.). However, eDRAM cells require periodic refresh operations to retain their data since the amount of electrical charges in capacitors reduces over time. The term ‘re- tention time’ of eDRAM cells means the time duration for which eDRAM cell can retain data. If an eDRAM cell is not refreshed at least once within the retention time, we cannot guarantee data in- tegrity of the eDRAM cell. Retention time directly affects refresh rates (i.e., how often refresh operations are required) and too fre- quent periodic refresh in eDRAM caches would incur huge perfor- mance and energy overhead in eDRAM-based last-level caches. On the other hand, as process technology continuously shrinks, process variation (PV) has also become a challenging issue for pro- cessor design. PVs typically incur device parameter fluctuations, which in turn cause delay and power variations in logic or mem- ory cells. In eDRAM cells, it is known that PVs mainly affect cell retention time, leading to non-uniform retention time distribu- tions [4] across cells. A common practice to tolerate PVs in eDRAM caches is to adopt conservative refresh rates (e.g., 50us [5]). It re- http://dx.doi.org/10.1016/j.micpro.2017.09.003 0141-9331/© 2017 Elsevier B.V. All rights reserved.