A geometry scalable approach to InP HBT compact modeling for mm-wave applications T. Nardmann 1 , P. Sakalas 1 , Frank Chen 3 , T. Rosenbaum 1 , M. Schroter 1,2 1 Chair for Electron Devices and Integrated Circuits, Technical University Dresden, 01062 Germany 2 ECE Dept., UC San Diego, La Jolla, CA 92093, USA 3 GCS Corporation, Torrance, CA 90505, USA Abstract - The bias and frequency dependent scaling of InP/ InGaAs HBTs with emitter width (and length) has been investigated for a 300GHz foundry process. It was found that the currents, capac- itances and resistances related to the emitter dimensions scale quite well. This allows the use of special test structures in combination with geometry variations to distinguish different physical effects and to accurately determine the external elements of the transistor as well as the thermal resistance independently of each other. The approach enables the generation of a geometry scalable set of HICUM/L2 model parameters for a large geometry range. The model was compared to experimental DC, AC and large-signal data of devices with different emitter geometry. The good agreement offers a much wider range of options for optimizing high-speed InP circuits. Index Terms - Heterojunction bipolar transistors, Indium-Phos- phide, Compact modeling, HICUM/L2. I INTRODUCTION InP HBTs are a promising contender for mm-wave circuits and systems and their extension into the THz realm [1, 2]. One of the obstacles of deploying InP technology in production circuit design is the lack of accurate transistor models (e.g. [3]). The demand for the latter has been documented by various attempts for improved compact models (e.g. [4, 5]). Since these attempts (incl. the use of VBIC) are based on the SPICE Gummel-Poon model (SGPM), which is not even adequate anymore for describing modern BJTs, the extensions tend to remain patchy and lack a solid physical basis. As a consequence, the effort for extracting the (too) many fitting parameters allows to provide model parameter sets for very few (typ. 3 to 5) different device sizes only. Also, the model accuracy suffers since a reliable extraction of parameters such as the base and collector resistance as well as the proper partitioning of capacitances is not possible based on data from just a single device geometry [6]. These problems severely limit circuit optimization and, thus, the exploitation of the true potential of InP HBT technology. Variation of especially the emitter width b E0 allows to separate many physical effects and to determine series resistances and capacitances of different device regions accurately, thus not only resulting in the model to accurately represent important time constants but also enabling statistical design. The latter is especially important for InP process technologies due to their relatively low volume and somewhat larger process variability (compared to e.g. SiGe BiCMOS technology). The issues described above (and several others) can be overcome with a physics-based geometry scalable modeling approach that has been used successfully for HICUM/L2 [7] by all major SiGe BiCMOS foundries for many years (e.g. [8, 9]. Rather than being limited to a single simulator (like special III-V HBT models), HICUM/L2 has been an industry-wide standard model since 2004 and has been available in a uniform and numerically stable implementation in all mainstream commercial circuit simulators. Most recently, HICUM/L2 has been applied to InGaAs/InP HBTs fabricated in various process technologies. First results using the simplified HICUM/L0 [7] were encouraging [10]. However, the lack of suitable test structures and, thus, the necessity of having to fit data of just a single device still did not allow an accurate determination of many elements of the equivalent circuit. In this paper, a geometry scalable modeling approach is presented, which enabled the switch to HICUM/L2. The corresponding experimental results are based on a special test chip designed and fabricated in a foundry process [11]. As a consequence of this work, similar circuit design capability as for Si-based technologies [12, 8, 9] can now be offered also for InP HBTs, hopefully aiding a more rapid deployment of this technology in prototypes and products. II GEOMETRY SCALABLE PARAMETER EXTRACTION In the equivalent circuit of HICUM/L2 each element represents a particular device region. The physical effects in that device region are captured by the analytical bias, temperature and geometry dependent description of the elements [7]. Since some geometry related effects can only be accurately described by quite sophisticated equations such as Green’s functions the geometry dependence is typically not included in the model card or even the Verilog-A model code. The “absolute” HICUM/L2 model parameters are thus usually generated from technology specific parameters, such as sheet resistances as well as saturation currents and capacitances per area and perimeter length, and the given design rules of a process [7]. While this approach guarantees physics-based values for the equivalent circuit elements, it does require a somewhat larger initial effort regarding test structure layouts and parameter extraction. In this work, a set of special test structures was designed and fabricated which allowed to determine the required technology specific parameters of all transistor regions separately. In addition, with clever layouts, e.g., the collector and base resistance can also be measured directly on some of the structures. The examples shown below illustrate the approach. The internal and external base resistance components R Bi and R Bx can be measured and also clearly separated using a tetrode