Role of Al2O3 Thin Layer to Improve The Switching Properties in Ta5Si3 Based CBRAM Device Dayanand Kumar, Rakesh Aluguri, Sridhar Chandrasekaran, Umesh Chand and Tseung-Yuen Tseng* Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 30010,Taiwan, *E-mail: tseng@cc.nctu.edu.tw Abstract The switching properties of the Ta5Si3 based CBRAM de- vice are investigated for nonvolatile memory applications. The resistive switching properties can be improved by in- serting a thin Al2O3 layer between the bottom electrode and Ta5Si3 layer. The Ta5Si3/Al2O3 double layer device with the 1 nm thin Al2O3 layer exhibits excellent memory performances, such as stable DC endurance up to 10 4 cy- cles during the test without degradation, good retention ability (>10 5 s) at a temperature of 130 0 C with more than 10 2 resistance ratio. 1. Introduction Conductive Bridge RAM (CBRAM) has been considered to be a promising candidate to replace NAND FLASH memory because of its high scalability, high retention, large memory window and low power consumption [1-3]. The re- sistive switching (RS) principle in a CBRAM device is based on the formation and rupture of the conductive filaments con- sisting of oxidation and reduction of metal (Cu+, Ag+) ions [4]. Bilayer based CBRAM devices are found to be exhibiting better memory characteristics such as stable switching volt- ages, on/off ratio, compared to the single layer devices by controlling the conducting filament (CF) size and position [5,6]. In this study, we investigate double layer CBRAM de- vice with the insertion of an Al2O3 layer between Ta5Si3 layer and bottom electrode to control the formation and rupture of the conductive filament, which shows highly stable switching characteristics with narrow fluctuations in set/reset voltages. 2. Experimental Detail A 20 nm thick Ti adhesion layer and a 50 nm thick Pt bottom electrode (BE) were deposited by electron beam evap- oration on SiO2/Si substrate. Al2O3 of thickness 1 nm, 3 nm and 5 nm were deposited on Pt BE by atomic layer deposition and then 10 nm thick Ta5Si3 was deposited by a radio-fre- quency (RF) magnetron sputtering at room temperature. Fi- nally, 4 nm Ta and 250 nm thick Cu top electrode were de- posited by sputtering to form Cu/Ta/Ta5Si3/Al2O3/Pt double layer CBRAM structure. 3. Result and Discussion The cross-sectional TEM image of the Cu/Ta/Ta5Si3/Al2O3/Pt double layer device are illustrated in Fig.1. The TEM image shows the clear and distinguished presence of various layers within the device. It confirms that the double layer device consists of Cu top electrode, 4 nm Ta adhesion barrier layer, 10 nm Ta5Si3 switching layer, 1-nm Al2O3 interfacial layer between Ta5Si3 and Pt BE. The typical forming process and DC sweep I-V curve of the single layer (SL) and double layer (DL) devices are shown in Fig-2, where both devices are showing bipolar resistive switching behavior. Fig-3 compares the distribution of resistance in HRS and LRS states during continuous switching upto 1000 sweep cycles. Significant fluctuations of both HRS and LRS are observed in the SL device, while it shows the narrower distribution in the DL device. Obviously, the uniformity of LRS and HRS can be improved by inserting a thin Al2O3 layer between the Ta5Si3 layer and BE. It indicates that the stochastic formation and rupture of CF in the SL device while the effective RS region is confined in the DL device at Al2O3/Pt interface so that the DL device possesses sharp distributions in LRS and HRS, leading to the stable RS characteristics. The RS charac- teristics of SL device and DL devices with different Al2O3 thicknesses are shown in Fig. 4. On the other hand, the wide fluctuations of the resistance in DL devices with 3 nm and 5 nm Al2O3 compared to that of 1 nm Al2O3 DL device are ob- served during continuous switching as shown in Fig. 5. This phenomenon is caused by the random formation and rupture of the conductive filament in the thicker Al2O3 film, which suggests that the region for rupture of the conductive filament is large. Fig. 6 and Fig. 7 show the DC endurance test for all devices which can well maintain its states for more than 10 4 cycles without any degradation in DL device with Al2O3 1 nm thickness. The non-volatility of data storage is further con- firmed by retention test measured at 130 0 C. The DL device shows good retention property at high temperature for more than 10 5 s, as shown in Fig. 8. 4. Conclusion The switching characteristics and uniformity of the Ta5Si3 based CBRAM device has been extremely enhanced with in- serting a thin Al2O3 layer between Ta5Si3 and BE. Enhanced on/off resistance ratio (>10 2 ) and endurance of (>10 4 ) is achieved without any degradation in the DL device due to the control of the formation and rupture of the CF at Al2O3/Pt in- terface. The two resistance states are stable over 10 5 s at 0.3 V without any observable degradation at 130 0 C, which demonstrates the good reliability of the DL device at higher temperature. These results indicate that the RS properties of the Ta5Si3 based device have been improved by inserting the 1 nm thin Al2O3 layer. Acknowledgement This work is supported by National Science Council, Tai- wan, under Project No. NSC 105-2221-E-009-134 -MY3. References [1] R. Waser and M. Aono, Nat. Mater., 6 (2007) 833. [2] U. Celano et al., Proc. IEEE IEDM, (2013) 574. [3] K. Ota et al., IEEE IEDM, (2016) 556. [4] I. Valov et al., Nanotechnology 22 (2011) 254003. [5] S. Yu et al., International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (2011) 1–2. [6] T. L. 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