4-channel Double S-shaped AWG Demultiplexer on SOI for CWDM Nurjuliana Juhari, P Susthitha Menon Senior Member IEEE, Abang Annuar Ehsan and Sahbudin Shaari* Member IEEE Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 UKM Bangi, Selangor, Malaysia nurjuliana@unimap.edu.my, susi@ukm.edu.my, aaehsan@eng.ukm.my, sahbudin@eng.ukm.my AbstractWe demonstrate the design, fabrication and characterization of silicon-on-insulator (SOI)-based Arrayed Waveguide Grating (AWG) with broad channel spacing of 20 nm (~2500 GHz) which has a unique double S-shaped pattern at the arrayed region. Beam propagation method (BPM) under TE polarization at a central wavelength of 2431GHz and Complementary-Metal Oxide Semiconductor (CMOS) technology are used to simulate and fabricate the AWG device with 340 nm thick top silicon (Si) guiding layer. Performance comparison of insertion loss and optical crosstalk between the simulated and fabricated AWG was discussed. SOI-based AWG is employed in the Coarse Wavelength Division Multiplexing (CWDM) system to investigate the functionality of the device at a system level as well as to analyse signal degradation using a bit- error rate (BER) analyzer when 10 Gb/s and 40 Gb/s data rates are applied. Keywords AWG; broad channel spacing; CMOS technology; CWDM system; SOI I. INTRODUCTION Arrayed Waveguide Grating (AWG) is a type of passive optical device that is widely employed in the wavelength division multiplexing (WDM) system. Different index- contrast materials such as silica-on-silicon, polymer, InP and silicon-on-insulator (SOI) can be used to develop the AWG devices. Recently, the idea to minimize the size of optical devices especially using high index contrast materials has become increasingly popular. However, the process of scaling down the size of the device to achieve an ultra-small design structure faces a few obstacles such as birefringence and high coupling loss. One successful AWG device fabrication has been reported by Zou. J et al. [1] in which crosstalk better than -14 dB and smaller birefringence of <3.5 nm is achieved using compensated silicon nanowire in CWDM optical interconnects. For optical communication application, optical devices must meet several requirements including having low insertion loss, low crosstalk (<-35 dB), high reliability and high temperature independence [2]. Thus, the selection of materials to fabricate optical devices is of a major concern. There have been a number of reports on the advantages of using SOI [2-4] which inspire us to fabricate an AWG device using this material. In this work, we developed a unique design structure of AWG demultiplexer that has a symmetrical S-shaped pattern at the arrayed region to comply with the broad channel spacing of 20 nm (~2500 GHz) on SOI substrate. Limitation possessed by the AWG-simulation tools caused the preference on the rib waveguide structure over other waveguide structures. We found that the best geometry for the rib waveguide structure to perform single mode profile under TE mode polarization was 75 nm for the etch depth and 700 nm for the core width. Successful design of the 4-channel SOI- based AWG was then employed in CWDM system to investigate the functionality of this device as a demultiplexer at a system level when 10 Gb/s and 40 Gb/s data rate was applied. This device was fabricated using a standard CMOS process technology and characterized using direct coupling technique. A comparison was also made between the transmission spectrum of the simulated and fabricated 4- channel AWG device. II. PROCEDURE OF DEVELOPMENT AWG-BASED SOI A. Design Parameter and Operation of AWG-Based SOI At the device level, the SOI-based AWG was designed using WDM-Phasar software and the simulation process was based on the algorithm of Beam Propagation Method (BPM) operated under TE mode polarization at a central wavelength of 1571 nm. The basic architecture of the AWG device consists of two free propagation regions (FPRs), an input/output waveguide and an arrayed waveguide with a constant path length difference (ǻL) of 7.118 ȝm. The AWG was constructed on a 340 nm thick Si guiding layer using the rib waveguide structure. To obtain single mode condition for this AWG device, a core width of 700 nm and etch depth of 75 nm were selected, resulting in an effective index of 3.38021. To make a compact and small-sized AWG layout, the bending radius of the arrayed waveguide must be close to 90°. However, for a broad channel spacing using S-shape design, decreasing the ending radius close to 90° is not preferable as it makes the arrayed waveguide highly lossy. In order to overcome this problem, the initial bending radius was increased until we achieved a 0.097 dB loss at the arrayed waveguide region. The end results were a first and last 424 ISBN 978-89-968650-4-9 July 1-3, 2015 ICACT2015