Journal of Electronic Testing https://doi.org/10.1007/s10836-018-5724-y Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning Parth Kansara 1 · Sharanabasavaraja Bheema Reddy 1 · Louay Abdallah 2 · Ke Huang 1 Received: 15 November 2017 / Accepted: 28 March 2018 © Springer Science+Business Media, LLC, part of Springer Nature 2018 Abstract Analog/RF alternate test schemes have been extensively studied in the past decade with the goal of replacing time-consuming and expensive specification tests with low-cost alternate measurements. A common approach in analog/RF alternate test is to build non-linear regression models to map the specification tests to alternate measurements, or to learn a pass/fail separation boundary directly in the space of alternate measurements. Among various challenges that have been discussed in alternate test, the model stationarity is a major bottle-neck that prevents test engineers from deploying it in long-term applications. In this work, we show that alternate test strategies can be implemented on-chip using analog/RF Built-In Self- Test (BIST) circuitry. Moreover, model refinement and dynamic adaptation can be achieved based on an automatic on-chip learning structure. Effectiveness of the proposed approach is demonstrated using experimental results from an RF Low Noise Amplifier (LNA) and its BIST implementation. Keywords Analog/RF testing · Alternate test · On-chip learning 1 Introduction The test cost reduction of analog/RF integrated circuits (ICs) has been extensively studies in recent years. The high cost of analog/RF ICs is mainly caused by the need of using expensive automated test equipment (ATE) to perform parametric measurements at high frequencies, the lengthy measurement setup and test times, and the inevitable manual process for setting up various types of measurements. Various approaches have been proposed to address the high cost of testing analog/RF circuits, including alternate test [3, 24, 26], machine learning-based approach [20], subset specification test selection [4, 5, 14, 18, 22], [13], wafer-level spatial correlation modeling [10, 12, 15, 16, 27], etc. Among existing test cost reduction Responsible Editor: M. Barragan  Ke Huang khuang@mail.sdsu.edu 1 Department of Electrical and Computer Engineering, San Diego State University, 5500 Campanile Drive, San Diego, CA, 92182-1309, USA 2 Dolphin Integration, 39 avenue du Granier, BP 65 - Inovallee, F38242 Meylan Cedex, France practices, alternate test has been widely studies due to its ability to accurately predict specification tests from a set of low-cost alternate measurements [24, 26]. The goal is to build non-linear correlation models that map the high- cost specification tests to a set of sophisticatedly selected low-cost alternate measurements. Once the models are established, for new Devices Under Test (DUTs), only low- cost alternate measurements are taken and used to predict specification tests or provide device pass/fail decision directly in the space of alternate measurements. Alternate test approach was originally proposed to pre- dict specification tests in an offline manner, i.e., external computational resources are used to build and store the cor- relation/prediction models and predict circuit performances or pass/fail decisions where these computational resources are available. In [9], baseband DSP processor was used to calibrate RF circuits based on a set of alternate measure- ments. In [25], a more compact and customized on-chip learning model was used to tune the performances of an RF LNA. A custom-designed analog neural network with mul- tilayer perceptron (MLP) structure was designed to tune the LNA to enhance its performances. However, the learning of the MLP in [25] was still performed based on external computational resources by communicating model param- eter updates with a host computer. While offline model