Enhancement of the device characteristics for nanoscale charge trap flash memory devices utilizing a metal spacer layer Hyun Woo Kim, Joo Hyung You, Dea Uk Lee, and Tae Whan Kim Department of Electronics and Computer Engineering Hanyang University Seoul, 133-791, Korea twk@hanyang.ac.kr Keun Woo Lee Research and Development Division Hynix Semiconductor Inc. Icheon-si, Kyungki-do, 467-701, Korea Abstract—Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased due to an increase in the fringing field and the coupling ratio resulting from the existence of the optimized metal spacer. The interference effect between neighboring cells was decreased due to the shielding of the electric field resulting from the existence of the metal spacer layer. Keywords-charge trap flash memory; interference effect; fringing field; coupling ratio I. INTRODUCTION Low-cost and high-density nonvolatile memory (NVM) devices have been currently receiving considerable attention for potential applications in portable devices [1-4]. Among the NVM devices, the charge trap flash (CTF) memory devices have been particularly interesting because of potential applications in mobile devices due to their excellent advantages of better scaling capability and smaller capacitive coupling interference between the adjacent cells in comparison with traditional floating gate flash memory devices [5]. However, the scaled down CTF memory devices still have inherent problems of the coupling interference between the adjacent cells in a bit-line direction [6-10]. The metal spacer layer existing in both sides of each memory cell closes to the Si substrate, resulting in an increase of the interference effect and fringing field on the channel area. However, a high electric field in an oxide layer between the metal spacer layer and the Si substrate is generated due to the small distance between the lower edge of the metal spacer and the Si substrate, resulting in a high gate leakage current [11]. Even though some works concerning the coupling interference phenomenon in the CTF memory devices have been conducted [10], systematic studies on the decrease in the coupling interference of the CTF memory devices utilizing a metal spacer with an optimum depth are very important for enhancing their device performance and density. This paper reports data for the device characteristics of the decrease of the interference effect between neighbor cells and to increase the fringing field on the channel surface between cells and the coupling ratio of the control gate for the CTF memory devices fabricated utilizing a metal spacer. The optimum size of the metal spacer layer for the CTF memory devices was determined by using a technology computer-aided design (TCAD) simulation tool taking into account the gate leakage current, the interference effects, and the fringing field effects. II. FABRICATION PROCESS Nanoscale metal-oxide-nitride-oxide-semiconductor, denoted by CTF memory devices, memory devices with a metal spacer layer are designed by using the conventional device process technology. The cleaned Si wafer is used as a substrate, as shown in Fig. 1(a). After the deposition of the tunnel oxide and the nitride layers, the nitride layer is etched, as shown in Fig. 1(b). After the deposition of the blocking oxide layer shown in Fig. 1(c), the blocking oxide layer is etched, as shown in Fig. 1(d). After the metal electrode is deposited, the source/drain is doped, as shown in Fig. 1(e). Finally, the gates and the source/drain contacts are patterned, as shown in Fig. 1(f). The thicknesses of the oxide-nitride- oxide layers formed on the substrate are 4/5/6 nm. The doping concentrations of the source region, the drain region, and the substrate are 3×10 18 , 3×10 18 , and 1×10 17 cm -3 , respectively. Fig. 1(f) shows the fabricated memory devices with a 30-nm channel length and a 14-nm length between neighboring cells. The metal spacer layer is formed to surround the nitride trap layer in the proposed CTF memory devices. The distance between the lower edge of the metal spacer and the Si substrate is defined as the metal spacer depth, as indicated in Fig. 1(f). The thickness of the blocking oxide and the oxide layers between the metal spacer and the nitride trap layers is 6 nm. The left and right cells in memory devices for conventional 978-1-61284-418-3/11/$26.00 © 2011 IEEE - 203 - P17