96 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 1, JANUARY 1999 Fig. 3. Circuit for evaluating . TABLE I MENTOR GRAPHICS SIMULATION PACKAGE RESULTS V. CONCLUSION A new approach is presented here for the computation of inner products which is an extension of both RNS and DA principles. This has resulted in an architecture which has the advantages of both the above systems. The circuit developed evaluates the sum in modular fashion without any conversion to the residue domain. The architecture is simple and uses fewer adders and memory compared to the conventional bit serial techniques and hence is amenable to VLSI. These advantages lead to practical implementation of this modular approach to many DSP algorithms. REFERENCES [1] C. N. Zhang and H. D. Cheng, “High speed single error correcting convertor for residue number processing,” in Proc. Inst. Elect. Eng., pt. E, vol. 138, no. 4, pp. 177–182, July 1991. [2] P. Burleson, “Polynomial evaluation in VLSI using distributed arith- metic,” IEEE Trans. Circuits Syst. II, vol. 37, pp. 1299–1304, Oct. 1990. [3] S. White, “Applications of distributed arithmetic to digital signal pro- cessing: A tutorial review,” IEEE ASSP Mag., vol. 6, pp. 4–19, July 1989. [4] A. B. Premkumar and T. Srikanthan, “A real time correlator architecture using distributed arithmetic principles,” in 4th NASA Symp. VLSI Design, Moscow, ID, Oct. 29–30, 1992, pp. 10.3.1–10.3.5. [5] P. L. Montgomery, “Modular multiplication without trial division,” Math. Comput. 44, vol. 44, pp. 153–169, 1985. [6] S. E. Eldridge, “A faster modular multiplication algorithm,” Int. J. Computer Math., vol. 40, pp. 63–68. [7] A. Wrzyszcz, D. Milford, and E. L. Daglass, “A new approach to fixed coefficient INEER product computation over finite rings,” IEEE Trans. Comput., vol. 45, pp. 1345–1355, Dec. 1996. A Novel Class AB First Generation Current Conveyor Alain Fabre, Hafid Amrani, and Herv´ e Bartelemy Abstract—A new design for a first generation current conveyor imple- mented from complementary bipolar transistors is introduced. Its input cell consists of two translinear mixed loops in parallel. The circuit that acts in AB class can process currents with magnitudes greater than the bias current and so generate very low harmonic distortion. It is characterized by low values for its parasitic input resistance and large 3 dB bandwidths. It can also be used with supply voltages as low as 1.2 V. Index Terms— Bipolar transistors, current conveyors, current mode circuits, low voltage, low power, translinear circuits. I. INTRODUCTION The first generation current conveyor (CCI), whose symbol is given in Fig. 1, is an active circuit commonly described using the following matrix relation: (1) It can be used, for example, to take out any current flowing to ground, through a very low parasitic impedance (as it is characterized by ). This is then duplicated with unity gain at high impedance on output [1], [2]. When the CCI operates in class AB, it can be biased from low dc current values and can process current signals having a magnitude larger than the bias current , with a low harmonic distortion [3]. To the best of our knowledge, all the CCI’s implemented from bipolar transistors which have been described up to now in available literature are class A devices only [1]–[3]. These are consequently restricted to the processing of input signals having magnitudes very much less than the bias current . In this way, also note that a theoretical schema for a bipolar class AB CCI is given in [2, pp. 171 and 174]. Nevertheless, any biasing current source has been indicated in this circuit and so this cannot lead to any possible practical realization. On the other hand, class AB first generation current conveyors implemented in CMOS technology have previously been described [4], [5]. Nevertheless, these implementations suffer from the relatively low performance which is inherent to CMOS circuits (for example, 3 dB bandwidths lower much less than with bipolar implementations). In addition, these CCI’s are all characterized by high input resistance values (299 , for example, for the circuit in [4], against an ideal value of zero for the CCI [1], [2]). In addition, Manuscript received August 6, 1997; revised July 20, 1998. This paper was recommended by Associate Editor G. A. DeVeirman. A. Fabre was with the Laboratoire d’Electronique, Ecole Centrale de Paris, 92295 Chatenay Malabry, France. He is now with the Laboratoire de Micro´ electronique, (IXL), TCS Group, Universit´ e Bordeaux I, 33405 Talence, France (e-mail: fabre@ixl.u-bordeaux.fr). H. Amrani was with the Laboratoire d’Electronique, Ecole Centrale de Paris, 92295 Chatenay Malabry, France. He is now with Texas Instruments, Mixed Signal Design Department, 06271 Villeneuve Loubet Cedex, France. H. Bartelemy was with the Laboratoire d’Electronique, Ecole Centrale de Paris, 92295 Chatenay Malabry, France. He is now with the Laboratoire d’Electronique, ISEM, 83000 Toulon, France. Publisher Item Identifier S 1057-7130(99)01474-3. 1057–7130/99$10.00  1999 IEEE