1482 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY2005 A Compact Triple-Band Low-Jitter Digital LC PLL With Programmable Coil in 130-nm CMOS Nicola Da Dalt, Member, IEEE, Edwin Thaller, Peter Gregorius, Associate Member, IEEE, and Lajos Gazsi, Member, IEEE Abstract—We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated pro- grammable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm . A new ar- chitecture is proposed which improves the authors’ previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for ap- plication as a low-jitter clock multiplying unit in digital intensive systems on chip. Index Terms—Digital control, digitally controlled oscillator, in- ductors, jitter, phase locked loops. I. INTRODUCTION H IGH-SPEED serial data transceivers in point-to-point connected systems typically use a phase-locked loop (PLL) as central clock source for a chain of data buffers (see Fig. 1). The incoming data stream is re-sampled by a clock and data recovery unit (CDR) and forwarded to the next data buffer. The PLL generates the reference clock for the re-synchroniza- tion unit as well as the core functionality. Serial data transceivers are traditionally very digital intensive applications, providing a harsh environment to low-noise analog frequency synthesizers. Besides, the design of those blocks is becoming increasingly difficult in the newest deep-submicron technologies, due mainly to decreasing supply voltages and de- terioration of the “analog” performances of transistors. A digital approach to the implementation of the synthesizer alleviates some of those problems and is also an ideal choice due to its robustness to external noise sources. A digital architecture for low-bandwidth frequency synthesis has been recently proposed [2]. This kind of architecture cannot be applied to serial data communications where a low-jitter PLL with a bandwidth in the megahertz range is required. In- deed in this case, the quantization noise produced by the digital phase/frequency detection and by the delta-sigma modulator Manuscript received November 12, 2004; revised February 2, 2005. N. Da Dalt and E. Thaller are with Infineon Technologies Austria AG, Design Center, Development Center Villach, A-9500 Villach, Austria (e-mail: nicola.dadalt@infineon.com). P. Gregorius and L. Gazsi are with Infineon Technologies AG, 81669 Munich, Germany. Digital Object Identifier 10.1109/JSSC.2005.847325 would not be sufficiently suppressed by the loop dynamics and would completely spoil the jitter performance of the PLL itself. In this paper, we present a digital approach for high-band- width synthesis based on the bang-bang PLL (BBPLL) principle [3], improving the concept presented in [1]. Although most of the high-speed BBPLLs implemented up to now use analog loop filters, we extend the concept and implement an all-digital ar- chitecture where the only block of analog nature is a digitally controlled LC oscillator. Advantages of this approach include friendly implementation in the newest digital CMOS technolo- gies, improved testability, robustness against PVT variations, low sensitivity to external noise sources, and easy loop filter pro- grammability. An additional motivation for this work is also given by con- siderations on spread-spectrum clocking (SSC). Indeed in most serial transceivers, a frequency modulated clock is used as pri- mary frequency reference to reduce electromagnetic interfer- ence (EMI) [4]. Different frequency modulation profiles are nor- mally used, like sinusoidal, triangular, or the nonlinear Lexmark modulation profile. The modulation scheme must remain undis- torted through the PLL, to avoid additional deterministic jitter or wander at the CDR sampling point. Due to the limited bandwidth, analog PLLs with spread-spec- trum input reference clocks exhibit a slight difference between the reference and feedback clock frequencies. As the input spread-spectrum clock frequency migrates from one extreme to the other of the modulation profile, the accumulation of the frequency difference can result in a significant amount of phase error within the system. This error will decrease the setup time and hold time margins at the data sampler within the CDR. Especially for systems where the reference clock has to be multiplied, the remaining tracking skew has to be minimized by increasing the closed-loop bandwidth of the PLL. Apart from the sinusoidal modulation, the commonly applied nonlinear modulation profiles contain higher order harmonic contents. The maximum frequency change happens when the modulation changes the polarity of its slew rate at the corners. To guarantee a minimum of distortion of all SSC spectral com- ponents, the phase angle of the PLL input-to-output transfer characteristic has to be kept constant within the frequency spec- trum of interest. Due to its nonlinear nature, a properly designed BBPLL can track the SSC achieving less phase distortion than an analog linear PLL. The synthesizer architecture presented here is not limited to serial data transceivers and can be used as general-purpose clock multiplying unit. 0018-9200/$20.00 © 2005 IEEE