Contents lists available at ScienceDirect Solid State Electronics journal homepage: www.elsevier.com/locate/sse Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress J. Park a , K.S. Jang a , D.G. Shin a , M. Shin b, ⁎ , J.S. Yi a, ⁎ a School of Electronic Electrical Engineering, College of Information and Communication Engineering, Sungkyunkwan University, 300 Cheoncheon-dong, Jangan-gu, Suwon 440-746, Republic of Korea b School of Electronics and Information Engineering, Korea Aerospace University, Goyang-city, Gyeonggi-do 412-791, Republic of Korea ARTICLE INFO The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Gate-induced drain leakage Off-state stress Charge trapping Defect creation Polycrystalline silicon thin-film transistor ABSTRACT Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (V gs ) and drain-source voltage (V ds ). Off-state bias stress was found to dramatically increase the threshold V gs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage V gs . 1. Introduction Polycrystalline (poly) silicon (Si) thin film transistors (TFTs) are generally used in active matrix display devices because of their multiple advantages [1]. The high field effect mobility of poly-Si TFTs is im- portant for peripheral circuits such as gate and emission drivers. Therefore, poly-Si TFTs can be easily integrated into display panels and are suitable for high resolution applications. Furthermore, the stability of poly-Si TFTs is very high under electrical and optical stress, making it a very popular device for use in active matrix organic light emitting diodes (AMOLEDs) and active matrix liquid crystal displays (AMLCDs) [2]. Despite these advantages, the poly-Si TFT is limited by high leakage current resulting from defect states in the poly-Si grain boundary. As the demand for display panels with ultra-high density resolution in- creases, there is an urgent need for efficient short-channel TFTs to form the individual pixels of AMOLED displays. This has prompted careful studies on the problem of leakage current in poly-Si TFTs [3]. Gate- induced drain leakage (GIDL) resulting from high drain-source voltage (V ds > 5 V) has been of particular concern, because the switching TFT of the AMOLED is normally operated under high gate bias conditions [4]. Several attempts to reduce the leakage current in poly-Si TFTs have been described in the literature [5]. Lightly doped drain (LDD) and offset structures can reduce the leakage current by reducing the electric field near the drain edge in the poly-Si channel, but instead, these methods reduce the field effect mobility to result in less drain current at on-state. Thermal and plasma treatments have also been reported to reduce the leakage current resulting from defects in grain boundaries of poly-Si [6], which need additional processing requiring more time and costs. For these reasons, they have not been widely applied in the fabrication of display devices. Another approach that has been proposed to reduce leakage current in p-type poly-Si TFTs is based on off-state stress [7,8].Off-state stress in a fabricated p-type poly-Si TFT is to apply positive gate-source vol- tage (V gs ) and negative drain-source voltage V ds of 5 to 15 V and -3 to -40 V respectively to the TFT for a short time. In our study, following the generation of off-state stress, the minimum leakage current was not found to have changed, but the threshold V gs (the V gs required to induce current, including GIDL) was considerably elevated. The GIDL current was correspondingly reduced and did not increase after the TFT was subjected to annealing at 250 °C. Importantly, field effect mobility and https://doi.org/10.1016/j.sse.2018.07.009 Received 9 April 2018; Received in revised form 2 July 2018; Accepted 18 July 2018 ⁎ Corresponding authors. E-mail addresses: mhshin@kau.ac.kr (M. Shin), junsin@skku.edu (J.S. Yi). Solid State Electronics 148 (2018) 20–26 Available online 19 July 2018 0038-1101/ © 2018 Published by Elsevier Ltd. T