Abstract— This paper overviews recent attempts at co-integrating nano-electro-mechanical systems (NEMS) with nanoelectronic devices aiming to add more functionalities to conventional Si devices in ‘More-than-Moore’ domain and also explore novel physical principles in ‘Beyond CMOS’ domain. Index Terms— Beyond CMOS, graphene, More than Moore, nanophonon, NEMS, quantum dot, single-electron transistor, suspended-gate I. CO-INTEGRATION OF NEMS AND MOSFETS FOR ‘MORE-THAN-MOORE’ APPLICATIONS LSI technology developed and matured over the past decades has been fully exploited to build the vast technology area of micro-electromechanical systems (MEMS). Along with a rapid expansion of the MEMS market, there have also been continuous efforts at making the MEMS smaller (Fig. 1) in order to boost the resonant frequency to GHz and beyond. The appearance of high-frequency nano-electro-mechanical systems (NEMS) is tempting enough for us to consider the co-integration of the NEMS and conventional silicon electronic devices (‘More than Moore’) because we expect such hybrid systems enhance scaling of functional density & performance while simultaneously reducing the power dissipation beyond the conventional CMOS-based systems. In addition, recent emergence of superior graphene-based NEMS (GNEMS) [1] provides more choice of building blocks for the hybrid systems. A variety of new hybrid NEM-MOS devices have recently been studied for advanced switch, memory and sensing applications (see TABLE I). A pioneering hybrid device is a Manuscript received March 22, 2011. This work was supported in part by the EU FP7 NEMSIC (Hybrid Nano-Electro-Mechanical / Integrated Circuit Systems for Sensing & Power Management Applications) project and SORST JST (Japan Science and Technology) and MEXT KAKENHI 18310097 and 16206030 Japan. H. Mizuta is with NANO Group, Electronics and Computer Science, Faculty of Physical and Applied Sciences, University of Southampton, Highfield, Southampton SO17 1BJ, U.K. and School of Materials Science, Japan Advanced Institute of Science and Technology (JAIST), Ishikawa 923-1292, Japan (phone: +44(0)2380 592852; fax: +44(0)2380 593029; e-mails: hm2@ ecs.soton.ac.uk, mizuta@jaist.ac.jp) M.A.G.-Ramirez, Z. Moktadir, Y. Tsuchiya are with NANO Group, Electronics and Computer Science, Faculty of Physical and Applied Sciences, University of Southampton, Highfield, Southampton SO17 1BJ, U.K. (*phone: +44(0)2380 592852; fax: +44(0)2380 593029; e-mail: hm2@ ecs.soton.ac.uk). S. Sawai, J. Ogi, S. Oda are with Quantum Nano Electronics Research Center, Tokyo Institute of Technology, Ookayama, Meguro-ku, Tokyo 152-8550, Japan suspended-gate (SG) FET [2] which features a movable gate electrode located on a conventional oxide / silicon substrate via an air gap. Thanks to unique electro-mechanical pull-in / pull-out operations, the SGFETs exhibit very abrupt electrical switching with a subthreshold swing much smaller than a theoretical limit of 60 mV/dec for MOSFETs as well as extremely low off current. The SGFETs therefore attract much attention in particular for power management applications. 1995 2000 2005 2010 2015 2020 1 10 100 1000 10000 Year Gate Length [nm] Resonator Length NEMS MEMS Characteristic Length (nm) Year MPU High Performance CMOS Gate Length - Printed MPU High Performance CMOS Gate Length - Physical More than Moore? Nano phononic system Beyond CMOS? CMOS CMOS nanotechnology era began - 1999 Fig. 1 Recent trend of MEMS/NEMS downscaling along with CMOS miniaturization. TABLE I. VARIOUS NEM-MOS HYBRID FUNCTIONAL DEVICES Suspended-gate(SG)FET z Abrupt switching with S < 60 mV/dec z Very low leakage z Power management applications  Self-buckling FG Memory  SG Si NanodotMemory z Seriously nonvolatile z Fast write/erase operation z Conventional silicon process compatible  Vibrating body FET  Resonant SG MOSFET z Extremely high mass responsibity of zeptogram/Hz order z Co-integration with SOI-MOSFET circuits NEM switch NEMmemory NEM sensor p-Si substrate S D nc-Si dots air gap suspended-gate (SG) tunnel oxide As for the memory applications, two types of novel high-speed and nonvolatile NEM-MOS hybrid memory Scaled Nanoelectromechanical (NEM) Hybrid Devices Hiroshi Mizuta, Member, IEEE, Mario A. Garcia-Ramirez, Member, IEEE, Zakaria Moktadir, Yoshishige Tsuchiya, Shunichiro Sawai, Jun Ogi, Shunri Oda, Member, IEEE V 978-1-4244-9021-9/11/$26.00 ©2011 IEEE