The rapid prototyping experience of an H.263 video coder onto FPGA Matı ´as J. Garrido a, * , Ce ´sar Sanz a , Marcos Jime ´nez b , Juan M. Meneses c a Departmento de Sistemas Electro ´nicos y de Control, Universidad Polite ´cnica de Madrid, E.U.I.T. Telecomunicacio ´n, Ctra. de Valencia, km 7, 28031 Madrid, Spain b SIDSA, PTM Torres Quevedo, 1. E-28760 TRES CANTOS, Madrid, Spain c Dpto. Ingenierı ´a Electro ´nica, Universidad Polite ´cnica de Madrid, E.T.S.I. Telecomunicacio ´n, Ciudad Universitaria s/n, 28040 Madrid, Spain Received 17 October 2003; revised 12 February 2004; accepted 6 October 2004 Abstract In this paper, the methodology used for prototyping an H.263 basic line video coder is explained. The coder is based on an architecture, which we have called MVIP-2, consisting of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware–software co-simulation using standard video sequences. All modules except the RISC have been synthesized and fitted onto an FPGA. The prototype has been tested in real-time using a commercial board with the RISC and the FPGA, a pattern generator emulating a video camera to generate the input sequences and a logic analyzer to test the H.263 output stream. We have used a classic design methodology with some improvements in order to carry out rapid system prototyping. With this improved methodology, a prototype can be obtained early in the design cycle allowing the debugging of some hardware and software components permitting others to be designed at the same time. In this paper we explain how this methodology has been applied to a complex design (MVIP-2). Despite some details being specific to this design, the main aspects of the methodology can be applied to other designs. q 2004 Elsevier B.V. All rights reserved. Keywords: H.263; FPGA; RISC; Rapid system prototyping 1. Introduction In the last 10 years, the evolution of the digital technologies, together with the establishment of a set of standards widely followed by the industry, such as MPEG-2 [1], MPEG-4 [2] and H.263 [3], has allowed the develop- ment of a wide range of video applications: digital TV, HDTV, VoD, videophone, videoconferencing, etc. The applications implemented in low rate channels, e.g. videophone, use low-resolution formats such as CIF (Common Intermediate Format: Spatial resolution of 360!288 pels and temporal resolution of 30 frames/s). Even so, the available bandwidth is usually rather lower than that needed for working with a minimum level of performance. The image compression techniques can drastically reduce the bit-rate needed to encode the digital video signals. Although a large quantity of useful techniques have been reported, nearly all applications are based on the hybrid encoding scheme shown in Fig. 1, which uses the discrete cosine transform (DCT), quantization (Q) and motion estimation and compensation (ME/MC) among other techniques to carry out a reduction in the spatial and temporal redundancies existing in any natural sequence of images. MVIP-2 is a flexible architecture which implements an H.263 video coder based on the hybrid encoding loop shown in Fig. 1. The architecture is made up of a core RISC that controls the scheduling of a set of specialized processors that implement the coder loop. Our medium term goal is to offer this architecture as a flexible IP core useful for inclusion in H.263, MPEG-2 or MPEG-4 video coder SoC, as this scheme, with some differences, is the basis of these 0141-9331/$ - see front matter q 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.micpro.2004.10.005 Microprocessors and Microsystems 29 (2005) 393–404 www.elsevier.com/locate/micpro * Corresponding author. Tel.: C34 91 336 5224; fax: C34 91 336 7801. E-mail address: matias@sec.upm.es (M.J. Garrido).