Nanoelectronic Architecture for Boolean Logic VWANI P. ROYCHOWDHURY, MEMBER, IEEE, DAVID B. JANES, MEMBER, IEEE, AND SUPRIYO BANDYOPADHYAY, SENIOR MEMBER, IEEE A nanoelectronic implementation of Boolean logic circuits is described where logic functionality is realized through charge interactions between metallic dots self-assembled on the surface of a double-barrier resonant tunneling diode (RTD) structure. The primitive computational cell in this architecture consists of a number of dots with nearest neighbor (resistive) interconnections. Specific logic functionality is provided by appropriate rectifying connections between cells. We show how basic logic gates, leading to combinational and sequential circuits, can be realized in this architecture. Additionally, architectural issues including directionality, fault tolerance, and power dissipation are discussed. Estimates based on the current–voltage characteristics of RTD’s and the capacitance and resistance values of the interdot connections indicate that static power dissipation as small as 0.1 nW/gate and switching delay as small as a few picoseconds can be expected. We also present a strategy for fabricating/synthesizing such systems using chemical self-organizing/self-assembly phenomena. The proposed synthesis procedure utilizes several chemical self-assembly techniques which have been demonstrated recently, including self-assembly of uniform arrays of close-packed metallic dots with nanometer diameters, controlled resistive linking of nearest neighbor dots with conjugated organic molecules and organic rectifiers. I. INTRODUCTION It is generally accepted in the solid-state community that conventional strategies for integrating electronic devices on a chip will not be suitable for nanometer-sized elements because of the minuscule size of the elements and the corresponding low power handling capacity, low gain, and low fanout. Accordingly, a number of proposals have ap- peared in the literature that envision novel architectures for nanoelectronic logic circuits. Most of these schemes purport to exploit discrete (single- or few-electron) charge inter- Manuscript received November 5, 1996; revised January 14, 1997. This work was supported in part by the Army Research Office under Grants DAAL03-G-0144 and DAAH04-95-1-0586, and in part by the Defense Advanced Research Projects Agency under the ULTRA program Contract 35918-OH. V. Roychowdhury is with the Electrical Engineering Department, University of California, Los Angeles, CA 90095 USA (e-mail: vwani@ee.ucla.edu). D. B. Janes is with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907 USA (e-mail: janes@yara.ecn.purdue.edu). S. Bandyopadhyay is with the Department of Electrical Engineering, University of Nebraska, Lincoln, NE 68588-0511 USA (e-mail: bandy@engrs.unl.edu). Publisher Item Identifier S 0018-9219(97)02729-1. actions between semiconductor or metallic dots [1]–[10]. Unfortunately, they all suffer from one or more drawbacks. References [3] and [4] propose a paradigm which is plagued by problems associated with unavoidable and ubiquitous background charge fluctuations that make the circuits error prone, [5] requires precise clocking control and lacks suf- ficient fault tolerance, while [7]–[9] proposes a system that is difficult to fabricate. References [1] and [2] 1 suffer from all the problems associated with [3]–[9] and additionally raise a serious concern in that logic signal cannot propagate unidirectionally from the input to output since the input is linked to the output by Coulomb interaction which is bidirectional (reciprocal). Bidirectional flow of signal does not distinguish between input and output terminals [7]–[15]. There are additional problems in this paradigm such as the lack of isolation between input and output and the problem of unbalanced logic gates which tends to generate wrong answers for certain configurations of gates [16]. In this paper, we propose and demonstrate a novel par- adigm for nanoelectronic implementation of Boolean logic that can potentially eliminate the above drawbacks. In this implementation, each computational cell contains nanoscale metallic dots formed into regimented, two-dimensional (2- D) arrays on an active substrate which possesses a non- linear, nonmonotone current-voltage characteristic. Logic functionality is achieved through charge exchange between the metallic dots. In order to demonstrate the feasibil- ity of making these circuits, we also outline a fabrica- tion strategy which exploits chemical self-assembly/self- organization techniques to realize the nanoscale elements and the interelement connections. It appears that all of the individual components of the enabling technology have already been demonstrated and what remains to be achieved is the combination of these components to synthesize the circuits described in this paper. While this is certainly a nontrivial task, it seems that proof of concept demonstra- 1 This scheme lacks unidirectionality and does not work (see [7]–[15] for a discussion of this issue). Recent modifications of this scheme, whereby each cell is accessed and clocked individually to realize adiabatic switching, provides unidirectionality but results in exceedingly slow speed. There is still the lack of isolation between input and output. Furthermore, it is not clear how “logically irreversible” gates described in this paradigm can be switched adiabatically. 0018–9219/97$10.00  1997 IEEE 574 PROCEEDINGS OF THE IEEE, VOL. 85, NO. 4, APRIL 1997