JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.11, NO.3, SEPTEMBER, 2011 http://dx.doi.org/10.5573/JSTS.2011.11.3.169 Linearity-Distortion Analysis of GME-TRC MOSFET for High Performance and Wireless Applications Priyanka Malik*, R.S. Gupta**, Rishu Chaujar***, and Mridula Gupta* Abstract—In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: g m1 , g m2 , g m3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model. Index Terms—Corner effect, linearity, MLGME, RF, TRC MOSFET I. INTRODUCTION Recent explosion in the demand for mobile telecom- munication, computing and multimedia applications has resulted in much interest in system on chip (SOC) applications based on all CMOS technologies due to their inherent low cost and high density. In sub-100 nm regime MOSFETs are the strong contenders for analogue RF applications in lucrative wireless communications market. Linearity assessment [1-3] is an important parameter in all RF systems which need to be tailored in order to ensure that the inter-modulation and high-order harmonics are minimal at the output. Although there are system level techniques to improve linearity, they all require complex circuitry [4]. A transistor-level linearization is more appropriate for power amplifiers in the portable systems, which requires an analysis of linearity behaviour at device level as a function of important design parameters. The present work concentrates on the extensive study for various recessed channel structures, i.e. RRC, TRC, GME-TRC and MLGME-TRC MOSFETs, for different dielectric configurations to optimize the linearity performance by developing a model and validating it with experimental and simulation results. The Recessed channel (RC) MOSFET [5-7] structures are considered as potential candidates to suppress and overcome short channel effects (SCEs), punch-through and DIBL effects even at gate lengths down to the sub-100 nm regime because negative junctions can be fabricated without any increase in the series resistance and hence, for use in Manuscript received May 5, 2011; revised Jul. 22, 2011. * Electronic Sciences, Delhi University, New Delhi, Delhi, India ** Electronics & Communication Engineering, Maharaja Agrasen Institute of Technology, New Delhi, Delhi, India *** Applied Physics, Delhi Technological University, New Delhi, Delhi, India E-mail : mridula@south.du.ac.in