A MIMO-ready Hardware Platform for Digital Voice Communication at 2.45 GHz Jo Verhaevert 1 , Patrick Van Torre 1 , Micha¨ el Braem 1 , Hendrik Rogier 1 1 Ghent University - imec, IDLab, Department of Information Technology (INTEC), Technologiepark-Zwijnaarde 15, 9052 Ghent, Belgium, jo.verhaevert@ugent.be Abstract—This paper documents the development of a hard- ware platform for digital voice communication in the 2.45 GHz band. The design is centered around an ADF7242 transceiver, applying IEEE802.15.4 modulation. Furthermore, the design works half-duplex and is capable to communicate alternating in both directions. On the transmit side, the sampled audio signal is processed by means of software written in C, running on the on- board microcontroller, which transmits the data to the transceiver over its SPI bus. On the receiving side, the opposite occurs. The received audio data goes to the DAC with a sample rate of 16 kHz, connected to an amplifier and speaker. Successful real-time digital voice transmissions were demonstrated with the prototype boards. Index Terms— Digital voice communication, ISM band, low bit rate, wireless technologies. I. I NTRODUCTION Communication is of paramount importance these days, especially digital real-time voice communication [1]. In this paper, the development of a hardware platform to digitize a voice signal and communicate this data on the 2.45 GHz band, applying IEEE802.15.4 modulation [2], is described. The main goal is to communicate half-duplex [3], similar to how a walkie-talkie works, but at a much higher frequency and fully digital [4]. The downside of operating at a higher frequency is a more limited range. But the benefits are a more compact system and the possibility to employ encryption. The block diagram of the hardware platform is given in Fig. 1. The hardware setup will be further explained in Section II. The software development is outlined in Section III where the C-code of the microcontroller is documented. The conclusions are drawn in Section IV. II. HARDWARE In this section, the hardware design will be further explained based on the block diagram in Fig. 1. This diagram presents the main architecture of the hardware platform, that can be divided into 5 parts namely microcontroller, audio/speech, I/O, RF and power supply. The power supply is not shown on the block diagram, but has been implemented in the main PCB design. In the rest of this section, the 5 different parts are extensively described. A. Microcontroller The brain of the system is a C8051F120 microcontroller by Silicon Labs [5]. Its processing speed can achieve 100 MIPS Fig. 1. Block diagram. (with an internal PLL). The controller includes an 8-bit as well as a 12-bit Analog-Digital Converter (ADC), two 12-bit Digital-Analog Converters (DACs) and hardware SPI support. The microcontroller operates on a 3.3 V power supply and can be programmed by means of JTAG [6]. B. Audio/speech The speech can be captured with the on-board microphone or with an external one connected through a 4-pin jack connector. After capturing the speech, the signal goes to a Programmable Gain Amplifier (PGA) [7] via an internal multiplexer that is controlled through software SPI. The ADC needs an offset in order to capture AC signals, which is achieved by adding external components to the PGA. After the amplification the signal passes through a first order LC circuit that functions as a low pass filter with a cutoff frequency of 22 kHz countering aliasing. After filtering, the signal is sampled by the 12-bit ADC of the microcontroller with a sampling frequency of 16 kHz [8]. brought to you by CORE View metadata, citation and similar papers at core.ac.uk provided by Ghent University Academic Bibliography