International Journal of Electrical and Computer Engineering (IJECE) Vol. 12, No. 4, August 2022, pp. 3530~3539 ISSN: 2088-8708, DOI: 10.11591/ijece.v12i4.pp3530-3539  3530 Journal homepage: http://ijece.iaescore.com A new method for self-organized dynamic delay loop associated pipeline with reconfigurable computing system Nandigam Suresh Kumar 1 , Dasari Vijaya Lakshmi 2 , Bejjanki Pooja Sree Prasanna 2 , Dodda Venkata Rama Koti Reddy 3 1 Department of Computer Science and Engineering, GITAM Institute of Technology, GITAM (Deemed to be) University, Visakhapatnam, India 2 Department of Computer Science and Engineering, GITAM School of Technology, Hyderabad, India 3 Department of Instrument Technology, College of Engineering, Andhra University, Vishakhapatnam, India Article Info ABSTRACT Article history: Received Jul 25, 2021 Revised Mar 17, 2022 Accepted Mar 30, 2022 The minimization of propagation delay between pipeline stages is very important in wave propagation through pipeline-stages. The propagation delay can be minimized by minimizing the number of stages in a pipeline. In the proposed design a dynamic stage control is imparted in the pipeline. The propagation delay can be optimized in any type of pipeline by controlling number of stages dynamically. The pipeline interpretation helps a lot to overcome the flaws due to not ready sequence (NRS) and synchronization problems. It is observed that, in the pipeline design the basic and actively involved pipeline techniques are concerned with different challenges like clock, throughput, cell area, and sizes. As the data throughput increases the number of stages in pipeline also needs to be increased to meet the desired goal. In the case of unpredictable data speed, the definite number of pipeline stages creates severe problems. In this work a dynamic pipeline is integrated where the number of stages is dynamically changing depending up on data speed. In dynamic pipeline technique the circuit cell area of reconfigurable computing system (RCS) will be reduced dynamically at low-speed data transmission. In the high-speed data communication, the data speed is managed and controlled by dynamic delay loops. Keywords: Dynamic delay Parallel processing Pipeline Propagation delay Reconfigurable computing- system Self-organized map This is an open access article under the CC BY-SA license. Corresponding Author: Nandigam Suresh Kumar Department of Computer Science Engineering, GITAM Institute of Technology, GITAM (Deemed to be) University Gandhi Nagar, Rushikonda, Visakhapatnam, Andhra Pradesh 530045, India Email: nskgitam2009@gmail.com 1. INTRODUCTION With the advent of field programmable gate array (FPGA) it became very easy provides provision to design and develop large circuits and systems on single board. In this paper the required components for the proposed method and the other existing techniques are analyzed, tested, and compared on FPGA Sparton 3E board. The main advantage with FPGA is complex architectures can be easily designed, emulated, and tested for different real time applications. In the present paper the concrete designs of registers, interrupt logic, pipeline, and counters are implemented with Xilinx FPGA. Flexibility, malleability, training, and adaptability are the characteristics of the present research work. This environment motivated to design dynamic delay loops, which are proportional to the input data rate. In the present system high speed data rates are obtained from real time environment such as digital tachometer which is interfaced with electrical motor speed measurement system. The speed of rotor is