Closed-Loop Spurious Tone Reduction for Self-Healing Frequency Synthesizers Florian Bohn, Kaushik Dasgupta, and Ali Hajimiri California Institute of Technology, Pasadena, CA 91125 Abstract — On-chip spurious tone detection and correction in an 8-12 GHz CMOS synthesizer is used to automatically reduce spurious output tones at different offset frequencies by up to 20dB. Using synchronous detection, sensitivity is limited by detection time only. The presented methods are generally applicable to frequency synthesizers and phased-locked loops in various applications. Index Terms — phase locked loop, frequency synthesizer, spurious tones, VCO reference spur, spur reduction techniques, spurious tone suppression, sampled loop filter I. INTRODUCTION Spurious tones in phase-locked loop (PLL) synthesizers are undesirable for many reasons: in radio transmitters, spurs are transmitted alongside the RF carrier, interfering with users in adjacent channels. In radio receivers, spurs down-convert signals in adjacent radio channels to base- band, causing interference and degrading sensitivity. In clock-and data recovery circuits that use PLLs (e.g. [1]), spurs can cause increased bit-error rates in the recovered data due to edge-transition timing inaccuracies in the recovered clock. In fractional-N synthesizers, reference spurs in the oscillator output are dithered alongside the main tone, resulting in increased synthesizer noise. Side-tone spurs in synthesizers are typically introduced through frequency-modulation (FM) of the carrier signal, and are more problematic than amplitude-modulated (AM) tones as gain limiting operations attenuate AM spurs. In PLLs, the voltage-controlled oscillator (VCO) is typically FM modulated by periodic disturbances of the control voltage due to the loop action. In practice, many techniques are employed to reduce the disturbance: use of sample-and-hold loop-filter [2], feedback-based methods to reduce charge-pump mismatch [3], methods reducing the VCO gain upon lock [4], and methods to adjust the timing of control voltage actuation with sub-sampling phase-detectors [5]. All of the above methods attempt to either minimize the control voltage ripple in an open-loop fashion or the resulting FM modulation. In this paper, we present a true closed-loop spurious reduction using sensing and actuation of the oscillator control voltage ripple to offset the effects of parasitic capacitance charge feed-through, process, device mismatch, and temperature sensitive variations directly. Fig. 1. – Closed-loop reduction of VCO control voltage ripple in the presented scheme: injected pulses approximate the inverse of the uncorrected control voltage, reducing overall spurious tone power, particularly in lower harmonic components that are difficult to filter. II. CONCEPT Figure 1 illustrates our approach conceptually: the VCO control voltage signal is digitally sampled for processing in a DSP unit. For actuation, a periodic correction signal (error signal) is added to minimize the AC disturbance on the control voltage. Ideally, the correction signal is the true inverse of the original, analog control voltage disturbance such that the sum of the two signals is zero. However, to reduce power and area overhead in the correction signal generator, the correction signal is approximated using narrow, digitally generated pulses. In steady-state, both the detected as well as the generated error signal are synchronized to the reference signal and, hence, periodic. Therefore, the periodically injected pulse contains fundamental and harmonic components of the reference frequency, and N injected pulses of controllable amplitude and phase provide 2•N degrees of freedom to control the amplitudes and phases of the first N harmonics of the injected signal. The remaining difference contains mostly high-frequency components that are strongly attenuated by the loop filter. Voltage Voltage Voltage 978-1-4244-8292-4/11/$26.00 ©2011 IEEE