Screening of Si–H bonds during plasma processing P. Srinivasan * , B. Vootukuru, D. Misra Department of Electrical and Computer Engineering, New Jersey Institute of Technology, University Heights, Newark, NJ 07102, USA Received 10 December 2003; accepted 15 March 2004 Available online 20 June 2004 Abstract This work investigates the screening of Si–H bonds at the Si–SiO 2 interface in an n-channel MOSFET due to plasma charging damage. Since CMOS devices are subjected to high field electron injection during plasma processing, this condition was emulated by subjecting the devices to current stress (both gate injection and substrate injection). With the source and drain terminals reverse biased by a screening potential during stress, representing the impact from source and drain antenna, a decrease in stress-induced interface state density formation was noticed. Observed interface state density D it before and after the high field injection, therefore, demonstrates an effective screening of the source and the drain edges. During gate injection the Si–H bond concentration, estimated using a model based on a simple first order kinetic equation, is inversely proportional to measured D it at effective screening potentials. In substrate injection, however, the Si–H concentration does not relate to D it creation. Similar trends were observed for transistors with different antenna ratios. Subsequent hot carrier stress confirms that the screening is mainly due to protected drain edges. These results suggest that effective screening of Si–H bonds is possible during plasma processing. Ó 2004 Elsevier Ltd. All rights reserved. 1. Introduction Plasma-induced wafer charging continues to receive considerable attention for CMOS transistors whose size has been drastically reduced due to its scalability. It is well known that the gate oxide of MOSFET experiences stress during plasma processing due to high field elec- tron injection, caused by Fowler–Nordheim tunneling. Depending upon the plasma potential distribution on the surface of the wafer, the injection could be either sub- strate or gate injection [1–3]. In addition, plasma charge damage effects can be enhanced or exacerbated depend- ing upon the direction, distance and size of the antennas connected to the drain, gate, source and substrate [4–6]. If these antennas are connected to source and drain (S/D) junctions, it can affect the damage magnitude of the CMOS gates significantly. It is because the floating potentials generated at these terminals can induce sig- nificant damage even with minimal non-uniformity in the plasma. A reverse biased voltage at the source and drain termed as screening potential, to simulate the impact of source and drain antenna, was applied at the S/D junc- tions while the devices were subjected to a current stress. The depletion region extension to channel region at the source and drain edges can impact the device degrada- tion. It is well known that the generation of Si dangling bonds during current stress contributes partly to the degradation of Si–SiO 2 interface [7–9]. However the processes that are responsible for the creation of Si dangling bonds during plasma damage processes have been the subjects of on-going investigations. In this paper, we have attempted to understand the variation of Si–H bond concentration at the Si–SiO 2 interface under high field stress when a screening potential exists. The devices were further subjected to hot electron stress after high field stress to confirm the effectiveness of screening on Si–H bonds at the drain edge. 2. Experimental setup The wafers studied in this work consisted of nMOS transistors processed using 0.25 lm CMOS technology. * Corresponding author. E-mail address: sp76@njit.edu (P. Srinivasan). 0038-1101/$ - see front matter Ó 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.05.017 Solid-State Electronics 48 (2004) 1809–1814 www.elsevier.com/locate/sse