AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation Nuno Lourenço, Ricardo Martins n , António Canelas, Ricardo Póvoa, Nuno Horta Instituto de Telecomunicações, Instituto Superior Técnico, Lisboa, Portugal article info Keywords: Analog integrated circuits Automatic layout generation Electronic design automation Layout-aware sizing Post-layout performance Robust design abstract This paper presents AIDA, an analog integrated circuit design automation environment, which imple- ments a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alter- native floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE s , SPECTRE s , ELDO s or CALIBRE s . & 2016 Published by Elsevier B.V. 1. Introduction Unlike digital circuits, where the low-level phases of the design process are automated using fairly standard methodologies, synthesis and layout of analog circuits is either a manual task or uses some sort of custom automated solution. Despite the huge advances in the last decades in terms of analog IC computer aided design (CAD) environments, e.g., provided by CADENCE s [1], Synopsys s [2] or Mentor Graphics s [3] companies, and also in terms of electronic design automation (EDA) solutions powered by innovative companies, such as, MunEDA s [4] and SOLIDO s [5], from the best of our knowledge there are still no established solutions addressing automatic layout generation and/or auto- matic layout-aware sizing. Therefore, despite analog design being currently supported by sturdy circuit simulators, layout editing environment and verification tools, there is still a great depen- dence of human intervention in all phases of the design process, resulting in a time-consuming and error-prone design flow [6]. This paper presents AIDA, an enhanced version of AIDA [7], an analog integrated circuit design automation environment. The new version addresses robust simulation-based circuit-level sizing with worst case process, voltage and temperature (PVT) corners accounted in the performance evaluation, automatic layout gen- eration and parasitic extraction capabilities. Combining all these modules together, results on an innovative layout-aware synthesis approach tailored for analog ICs. The paper is organized as follows. In Section 2 the existent solutions for analog design automation, focusing on most recent R&D efforts on layout-aware sizing, are overviewed. In Section 3, the newest advances in AIDA environment are properly intro- duced, while Section 4 discusses the integration in the design flow, and the effort required by the designer to use and interact with the proposed automatic layout-aware sizing tool. In Section 5 the case studies are presented, and finally, in Section 6, the conclusions drawn. 2. Related work on analog design automation Design automation solutions are crucial to efficiently explore the design space and reduce designers' efforts. In this Section, the major solutions provided by CAD vendors that offer some level of automation to analog IC design are briefly outlined, as introduc- tion to the most recent R&D performed on layout-aware sizing methodologies. Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi INTEGRATION, the VLSI journal http://dx.doi.org/10.1016/j.vlsi.2016.04.009 0167-9260/& 2016 Published by Elsevier B.V. n Corresponding author. E-mail addresses: nlourenco@lx.it.pt (N. Lourenço), ricmartins@lx.it.pt (R. Martins), acanelas@lx.it.pt (A. Canelas), rpovoa@lx.it.pt (R. Póvoa), nuno.horta@lx.it.pt (N. Horta). Please cite this article as: N. Lourenço, et al., AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, INTEGRATION, the VLSI journal (2016), http://dx.doi.org/10.1016/j.vlsi.2016.04.009i INTEGRATION, the VLSI journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎