Vertical III-V Nanowire Device Integration on Si(100) Mattias Borg, † Heinz Schmid,* ,† Kirsten E. Moselund, † Giorgio Signorello, † Lynne Gignac, ‡ John Bruley, ‡ Chris Breslin, ‡ Pratyush Das Kanungo, † Peter Werner, § and Heike Riel † † IBM Research-Zurich, Sä umerstrasse 4, 8803, Rü schlikon, Switzerland ‡ IBM Thomas J. Watson Research Center, 1101 Kitchawan Road, Yorktown Heights, New York 10598, United States § Max Planck Institute of Microstructure Physics, Weinberg 2, 06120 Halle, Germany * S Supporting Information ABSTRACT: We report complementary metal-oxide-semi- conductor (CMOS)-compatible integration of compound semi- conductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO 2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process. KEYWORDS: Nanowires, III-V semiconductors, InAs, GaAs, Si, integration I ntegration of group III-V semiconductors on Si has become a vibrant field of research because of the possibility to further improve the performance of transistors in the next generation of CMOS circuits and to integrate laser light sources on Si for on-chip optical communication. 1 In particular the materials, InGaAs and InAs, which have high charge carrier mobilities and a direct bandgap, are among the most promising candidates. 2 While the superior device performance of these materials over that of Si has already been demonstrated, 3-5 a viable method for integrating them onto a Si platform still remains a key obstacle. Heteroepitaxy of III-V semiconductors on Si with low defect density has been pursued through the use of buffer layers, 6-8 wafer bonding, 9-11 and by promoting the formation of an interfacial misfit dislocation array to suppress the formation of threading dislocations. 12 It is also recognized that defects stemming from the joining of dissimilar materials can be reduced by patterning the substrate in various ways. Patterned substrates can act as dislocation sinks, 13 enable strain relaxation at the nanometer scale, 14,15 and can be used to direct the growing crystal away from the defective heterointerface. 16,17 Although the defect density is reduced with these techniques, threading dislocation densities on the order of 10 9 cm -2 are still reported. 18 Other approaches to locally integrate III-V materials on Si are based on nanowire epitaxy using catalyst particles 19,20 or selective area epitaxy. 21,22 Although strain relaxation is efficient in nanowire epitaxy, III-V nanowire growth in directions other than ⟨111⟩ has only been observed by the use of catalyst particles for a limited range of growth conditions and yield. 23,24 Thus, despite intensive efforts, a scalable and epitaxial integration method that provides material with sufficiently low defect densities, and is compliant with industry-standard Si(100) substrates, has yet to be demonstrated. Here we report on the local integration of InAs and GaAs vertical nanowires epitaxially grown on a variety of Si substrate orientations as well as on nanocrystalline (nc) Si, using SiO 2 nanotube templates to guide the growth. Our process is completely CMOS-compatible, independent of substrate orientation and with demonstrated scalability at least down to 25 nm nanowire diameter. We determine the top-facet morphology of InAs nanowires of various crystal orientation, assess the crystal structure of [110]-oriented InAs nanowires by transmission electron microscopy (TEM), and investigate the optical properties of GaAs nanowires by photoluminescence (PL) measurements. We also demonstrate vertical Si-InAs nanowire tunnel diodes fabricated on industry-standard Si(100) substrates and evaluate the homogeneity and robustness of the method from their performance. Figure 1a-d displays scanning electron microscopy (SEM) images of InAs nanowires grown on exactly (±0.5°) oriented Si (100), (110), (111), and (112) wafers. The nanowires are vertically oriented, regardless of the substrate orientation. To accomplish this, nanowire growth was guided within SiO 2 Received: December 20, 2013 Revised: March 7, 2014 Published: March 14, 2014 Letter pubs.acs.org/NanoLett © 2014 American Chemical Society 1914 dx.doi.org/10.1021/nl404743j | Nano Lett. 2014, 14, 1914-1920