926 IEEE TRANSACTIONS ONNANOTECHNOLOGY, VOL. 13, NO. 5, SEPTEMBER 2014 Suitability of the FinFET 3T1D Cell Beyond 10 nm E. Amat, C. G. Almud´ ever, N. Aymerich, R. Canal, and A. Rubio Abstract—The performance of the 3T1D-DRAM cell beyond 10-nm technology node is investigated when the memory cell is based on nonplanar multigate devices, i.e., FinFETs. Moreover, for completeness, the cell is analyzed in both SOI and bulk-based Fin- FETs. While relevant process variation robustness is observed in SOI-based FinFETs, 10× lower impact than for bulk-based ones. In order to improve the variability robustness of bulk-based Fin- FET cell, we propose a dual-V T strategy to enhance the dynamic cell behavior. Index Terms—FinFET, DRAM, variability and temperature. I. INTRODUCTION V ERTICAL multiple-gate devices, FinFETs, have emerged as promising candidates to substitute planar CMOS tech- nology for very large-scale integrated (VLSI) circuits beyond 20 nm, due to its higher potential to push forward the integration limits [1]. Among other advantages, the key ones are lower short- channel effects impact, steeper subthreshold slope, and reduced variability impact [1]. The FinFET can be presented as a device with two electrically coupled gates that can implement two dif- ferent configurations: shorted-gate (SG) and independent-gate (IG). The first one is based on an interconnection between front and back-gate that presents better short-channel scaling, since it provides a tighter control of the channel and smaller subthresh- old swing that results in lower leakage current [1]. On the other side, IG FinFETs provide a feasible device V T -control; authors have pointed out its challenging fabrication for large-scale IC applications in [2]. Nonetheless, there is still a debate today about the most reliable and adequate nonplanar multigate de- vice substrate, SOI or bulk [3]. Both achieve comparable device characteristics and dimensions reduction [4]. But SOI FinFETs show better variability tolerance [3] since they have an almost undoped channel, while bulk-based FinFETs are built on bulk wafers that have lower cost and defect density [4] as well as moderate self-heating effect [5]. Meanwhile, nowadays, random process variations are of par- ticular concern in memories because they are typically designed using minimum feature sizes for density reasons. In this sense, the almost undoped channel of the FinFET devices involves the Manuscript received November 14, 2013; revised April 29, 2014; accepted March 25, 2014. Date of publication June 24, 2014; date of current version September 4, 2014. This work was supported by the European TRAMS project (FP7 248789), the Spanish MINECO (JCI-2010-07083, TEC2008-01856 and TIN2010-18368 with the additional participation of FEDER founds) and par- tially supported by the 2012 Intel Early Career Faculty Honor program. The review of this paper was arranged by Associate Editor F. Lombardi. The authors are with the Electronic Department, Universitat Polit` ecnica de Catalunya, Barcelona 08034, Spain (e-mail: esteve.amat@upc.edu; carmen.garcia.almudever@upc.edu; nivard.aymerich@upc.edu; rcanal@ac. upc.edu; antonio.rubio@upc.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TNANO.2014.2332180 random doping distribution (RDD), traditionally stated as the largest source of variability for bulk devices, that can be con- sidered negligible. In consequence, other sources of variability, e.g., work function fluctuation, gate edge roughness (GER), fin edge roughness (FER), and metal grain granularity (MGG), have taken a major role on the device fluctuation [3], [6], [7]. In the context of memory systems, the well-established 6T-SRAM cell is highly influenced [8], and it presents significant speed degradation and cell instability [8], [9]. In this scenario, the 3T1D is a promising memory cell to be considered as a VLSI systems candidate [10]. Although the 3T1D cell is also affected by the process variations, they do not have a big impact on the operating frequency, unlike 6T [8]. Moreover, 3T1D provides extra advantages: lower cell area, nondestructive read process (in contrast to the conven- tional 1T1C-DRAM), and large retention time. Thus, the 3T1D cell has been presented as a suitable memory cell for memory caches [8]. In this context, fast access times are required while low retention times are architecturally masked. Additionally, the memory storage node is a capacitor, where the nonlinear gate capacitance of the gate diode provides a gain that leverages the internal voltage gain allowing a low-voltage bit-line oper- ation as well as nondestructive read [11]. Note that 3T1D cell is a Dynamic RAM, i.e., it stores temporarily the data. In order not to lose the contents and to hold data for extensive periods, a periodic refresh is required [8]. It is worth noting that we have previously studied the impact of the device variability in planar bulk CMOS sub-22-nm 3T1D memory [12], and a cell malfunction behavior was observed at this device dimensions. In particular, we observed that the device fluctuation of the write access transistor has a significant influence on the overall cell performance and, especially, in the retention time, since its small threshold voltage (V T ) leads to an elevated leakage current. In order to overcome this last drawback, a dual-V T strategy (i.e., different V T values in the same circuit) is proposed to reduce the leakage of different circuits/memories [13]. The dual-V T technique is optimally implemented by metal gate work func- tion engineering for a more convenient cell performance [13]. Furthermore, the FinFET introduction in 3T1D memories can result in a more reliable cell performance. In this sense, a fully 32-nm SG-FinFET 3T1D cell was studied [11], [14], showing better chance of scaling and excellent robustness to variations. Nonetheless, in this study, we have implemented the dynamic cell with smaller FinFETs (10 nm). FinFET technology has been also introduced in 6T-SRAM cells, and promising results are shown [15]–[17] in terms of cell variability robustness and performance. Furthermore, the dual-V T strategy has been used in a 6T cell showing it feasibility [18]. In this study, we present a study about the reliability impact of the 3T1D-DRAM cell when it is implemented with Fin- FETs beyond 10 nm. We have structured the paper as follows: 1536-125X © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information.