Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects G. Cardoso Medeiros 1 & E. Brum 1 & L. Bolzani Poehls 1 & T. Copetti 2 & T. Balen 2 Received: 11 October 2018 /Accepted: 1 March 2019 # Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-scaled devices. However, FinFET-based SRAMs can also be affected by resistive defects that may lead to dynamic faults, which are considered one of the most important causes of manufacturing test escape in deep-submicron technologies. Hence, this paper proposes to evaluate the impact of temperature on the dynamic faulty behaviour of 20 nm FinFET-based SRAM cells affected by weak resistive defects. In more details, the critical resistances and the number of consecutive operations necessary to sensitize faults at the logic level are investigated. Additionally, the concept of Dynamic Behaviour Window (DBW) is defined. Results showed that temperature plays a major part in the sensitization of dynamic faults. Thus, the occurrence of dynamic faults has been mapped combining temperature as well as defect size, and the DBW has been defined considering resistive defects. The proposed evaluation helps to understand the behaviour of dynamic faults in memory cells even better and therefore can be used to improve the test procedures for deep-scaled FinFET memory devices. The proposed analysis has been performed using HSPICE simu- lations adopting a 20 nm Predictive Technology Model (PTM) of multi-gate transistors based on bulk FinFET. Keywords FinFET . SRAMs . Resistive-defects . Temperature 1 Introduction During the last decades, advances in Complementary Metal- Oxide Semiconductors (CMOS) nano-scale technology allowed the miniaturization and integration of hundred million transistors into a small silicon area. The evolution of Metal- Oxide Semiconductor Field Effect Transistors (MOSFETs) technology in Very Deep Sub-Micron (VDSM) circuits has accurately followed Moore’ s Law predictions. However, this miniaturization also presented many challenges on conven- tional planar MOSFET transistors and significant changes to the paradigms of digital and analogue circuit design were required. Due to the growing leakage and short-channel prob- lems, shrinking MOSFET technology below 20 nm was not feasible anymore, making it impossible to continue the mini- aturization according to Moore’ s Law [1]. Moore’ s Law has been extrapolated in three domains, named More Moore, Beyond CMOS and More-than-Moore [2]. In this scenario, FinFET technology has emerged as the most promising alternative to continue CMOS scaling due to its reduced short channel effects, electrostatic characteristics [3, 4], and its compatibility with standard CMOS manufactur- ing process [4, 5]. In more detail, FinFET technology fulfils all the high performance requirements imposed by modern Integrated Circuits (ICs) guaranteeing the CMOS continuous miniaturization, known as the More Moore domain [6]. FinFET technology is already replacing planar CMOS transis- tors in state-of-the-art ICs – major microelectronics companies have started to use FinFET transistors in their high-end pro- cessors during the last years. In parallel, the always-increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) have become the main contribu- tor to the overall area of Systems-on-Chips (SoCs), bringing Responsible Editor: P. Girard * L. Bolzani Poehls leticia@poehls.com 1 School of Technology, Pontifical Catholic University of Rio Grande do Sul – PUCRS, Porto Alegre, Brazil 2 Graduate Program on Microelectronics, Federal University of Rio Grande do Sul – UFRGS, Porto Alegre, Brazil Journal of Electronic Testing https://doi.org/10.1007/s10836-019-05784-1