IJCSNS International Journal of Computer Science and Network Security, VOL.8 No.9, September 2008 250 Manuscript received September 5, 2008. Manuscript revised September 20, 2008. Design and Performance analysis of efficient bus arbitration schemes for on-chip shared bus Multi-processor SoC Neeta Doifode 1 , Dinesh Padole 2 ,Dr. P.R. Bajaj 3 G.H. Raisoni College of Engineering, Nagpur, India, Summary In the resource sharing mechanism of multi-processor SoC, the on-chip communication architecture plays an important role and directly affects the performance of SoC. The traditional shared bus arbitration schemes show the several defects such as bus starvation, and low system performance. In this paper, we discuss about the static & dynamic Lottery Bus algorithms. ATM switch architecture is also discussed which is based on a probability and uses an adaptive ticket value method to solve the problem of Lottery Bus arbitration schemes. The discussed architectures are modeled using VHDL, and simulated in ModelSim software. The comparison of these three arbitration schemes with respect of performance parameters such as average latency, acceptance rate & bandwidth waiting time are presented. The simulation results shows the ATM switch architecture decrease the bus request latency by 49% Key words: System-on-Chip (SoC), Bus Arbiter, VHDL, Multiprocessor 1. Introduction SoC is a technology that integrates heterogeneous system components such as microprocessor, memory ,logic and DSPs into a single chip[1&3].The performance of multiprocessor systems depends more on efficient communication among processors and on the balanced distribution of computation among them, rather than on pure speed of processor[9].Although there are many possible communication architectures, shared bus is very popular in small number of processors system for its simplicity and area efficiency .The arbitration plays a crucial role in determining the performance of bus based system as it assign the priorities with which processor is granted the access to the shared communication resources. An efficient contention resolution scheme is required to provide fine-grained control of the communication bandwidth allocated to individual processor and avoid starvation of low priority component. In this paper, the Lottery Bus algorithm such as static and dynamic lottery Bus algorithm are briefly discussed. Also the ATM switch architecture based on the probability bus distribution algorithm is discussed to solve the problem of Lottery Bus algorithm. The comparison of these three arbitration schemes with respect of performance parameters such as average latency, acceptance rate, bandwidth waiting time are discussed 2. System on Chip Communication Architectures: A Review 2.1. Static Fixed Priority Algorithms Static fixed priority is a common scheduling mechanism on most common buses [7&2].In a static fixed priority scheduling policy, each master is assigned a fixed priority value. When several masters request simultaneously, the master with the highest priority will be granted. The advantage of this arbitration is its simple implement and small area cost. The static priority based architecture does not provide a means for controlling the fraction of communication bandwidth assigned to a component. If masters with high priority requests frequently, it will lead to the starvation of the ones with low priority. 2.2 .TDM/Round-robin algorithm Time division multiplexed (TDM) scheduling divides execution time on the bus into time slots and allocates the time slots to adapters requesting use of the bus[4-7]. Each time slot can span several physical transactions on the bus. A request for use of the bus might require multiple slot times to perform all required transfers. However, in this architecture, the components are provided access to the communication channel in an interleaved manager, using a two level arbitration protocol.