International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 – 8958, Volume-8 Issue-6, August 2019 2604 Published By: Blue Eyes Intelligence Engineering & Sciences Publication Retrieval Number F8754088619/2019©BEIESP DOI: 10.35940/ijeat.F8754.088619 Abstract: Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of Backbox model based top level hierarchical floorplanning based physical design. The main aim of this project is to reduce the number of instances which are not necessary in the top level chip floor planning which reduces peak memory for the design and also reducing CPU run time for getting proper prototype design in the top level ASIC design and estimate the congestion in the design at initial stage and modify floor planning to obtain quality of prototype model in the floorplanning. This project is designed on cadence encounter tool. Index Terms: Heirarchical floorplanning, Blackbox model, Instances, VLSI, Physical design. I. INTRODUCTION Physical design is the process of creating the physical layout of the corresponding to the netlist. In the physical design process various stages are available. They are floorplannig, power planning, placement, clock tree design, global routing, detailed routing, timing verification for each and every stage in design and finally getting the GDSII file. As a greater number of devices integrated on the single silicon chip the complexity of the design increases day by day which is appearing in the nano scale design [2]. Floorplanning is the most important step in the PD flow. The quality of the Floorplanning is effect on further stages of placement, cts, routing [3]. If the Floorplanning is not in good manner then further stages are facing various problems like less availability of routing resources, it is difficult to meet the desire timing requirements which results in more number of iterations and takes more memory for the design and CPU runtime. Revised Manuscript Received on August 25, 2019. Correspondence Author Rajasekhara Reddy Kallam, Electronics and Communication Engineering, LakiReddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna Dt, Andra Prasesh INDIA Srinivasulu Gundala, Professor, Electronics and Communication Engineering , LakiReddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna Dt, Andra Prasesh INDIA Floorplanning is initial stage of any hierarchical physical design. The main goal of the floor planning is to create a finalized prototype. prototyping involves multiple iterations with focus on the routability and timing constraints [3]. Generally, the top-level VLSI chip planning is done by using different prototypes, for each prototype estimate congestion and timing constraints based on quick placement and global routing. There are few millions of gate-level logic units, R.Otten proposed a method called “Automatic floorplan design" in the year of 1982 [4]. Many of new algorithms and methods are implemented in the Floorplanning stage, such as simulated annealing algorithm in [5] and incremental guided Floorplanning algorithm with effectively reduce the IR-drop violations with the help of B*-tree representation in [6], and P/G(power and ground) network and Floorplanning method for fast design convergence in [7]. Even though by using this algorithms and methods taking more amount of time and doing more iterations. Using a method of Flex model-based method reduces unnecessary instances which improves run time and CPU in chip planning stage [1]. However, it is also taking more iterations. To Improve more effective run time and peak memory usage we are using Blackbox model-based floor planning which will reduce runtime and CPU peak memory. This project is done on Cadence encounter tool. II. EXISTING METHOD Flexmodel based heirarchical Floorplanning with active logic reduction technology is one of the method in the design VLSI heirarchical floor planning. In the flexmodel based heirarchical Floorplanning uses Flexfillers for masking the unwanted instances in the design. Flexfiller is used to mask the various combinational logic levels between reg2reg logic path in whole design which results in reducing the instances during top level chip planning. If the number of instances are reducing then the EDA tool take less time to get required optimized top level floor planning. After completing top level chip heirarchical Floorplanning with required prototype the Flexfillers are removed and remaining stages i.e. partitioning, individual block design, assemble the design, optimize the design and signoff are same as traditional hierarchical physical design flow. Rajasekhara Reddy Kallam, Srinivasulu Gundala Ananth Kumar Vissampalli 1 , Rani Rudrama Kodali 2 BlackBox Model Based VLSI Hierarchical Floorplanning