VOL. 15, NO. 14, JULY 2020 ISSN 1819-6608 ARPN Journal of Engineering and Applied Sciences © 2006-2020 Asian Research Publishing Network (ARPN). All rights reserved. www.arpnjournals.com 1552 DEVELOPMENT OF OPTIMIZED VOLTAGE LEVEL SHIFTER FOR NANOSCALE APPLICATIONS Srinivasulu Gundala 1 , Kommu Siddhartha Mavovarakumar 2 , Kona Naga Nandini 3 , Sravani Gantala 4 , Javisetty Ravi Sankar Varma 5 and Chakrala Navya 6 1,3,4,5,6 Department of ECE, Lakireddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna District, India 2 Department of CSE, Lakireddy Bali Reddy College of Engineering (Autonomous), Mylavaram, Krishna District, India E-Mail: srinivasulugundala46@gmail.com ABSTRACT Multi voltage clustered systems are the basic and vital power decrease techniques, these approaches employs Level shifters to interconnect “Multiple voltage domains” to reduce power in core/module level. The Level Shifter may considered as area, power and delay overheads when its own power, delays are high. We proposed a circuit technique with broad shifting range for Nanoscale applications. In this brief, for minimization of current contention to attain both efficient and robust level shifting, we introduced new LS with series of Diode current limiters, which minimizes the dynamic power and propagation delay. Implementation of the LS in 130nm technology makes the proposed LS in accomplishing both efficient and robust level shifting from deep sub-threshold voltage 0.15V to supply voltage 1.25V. The developed LS have attained an average propagation delay of 6.20ns, Energy efficiency of 26.5fJ. . Keywords: level shifter, power, delay, near-threshold, current limiter. 1. INTRODUCTION The uses of portable/handheld electronic gadgets like cellular phones, multimedia cameras, and pace makers are increasing rapidly day by day, and power consumption has to be reduced at system level to attain more user satisfaction. The ultimate solution is Multi VDD systems and System-on-Chip (SoCs) [1-3]. These are becoming more popular and common in many practical applications. Such a multi VDD and SoCs are needed to be operated with different supply voltages. For such compute theory, energy and power consumptions are crucial design elements. Both the power and Delay of a digital IC depends on its supply voltage. Figure-1. DCVS level shifter. Level Shifter (LS) is necessary and widely placed among various voltage designs for multiple supply voltage domains. Considering this, to operate in a broad dynamic range the LSs are chosen, at which the near-threshold input scenarios are contained in it. Majorly, the previous LS design which is based on the “Differential Cascade Voltage Switch (DCVS)” LS design in Figure-1 is difficult for shifting from near-threshold to super- threshold, because of the prior current contention caused which is due to the limited drivability of the pull down devices operated in the near threshold region. Generally, when the input signal scales below threshold voltage, the conversion failure is caused due to the contention. 2. REVIEW ON EXISTING LEVEL SHIFTERS By utilizing intermediate power rails in multistage LS circuit design [4] which reduces the contention in every stage. In general, generation of the multiple voltage supplies through regulators is expensive in many aspects. Thus the area and power overheads are overpowering due to boosting of pull down devices channel width, which is beneficial for good performance and efficient level conversion operation by using well desired appropriate design techniques [5]. The LSs in [6-12] useful in wide range shifting application, and having a provision for bidirectional level shifting, balancing transition time delays, and it poses DCVSL kind of circuit topology utilizes dual power supplies. Being dual power supplies routing congestion may occurs at physical design. The DCVS LS acts as a ratioed circuits and the contention among pull-up and pull- down networks turn out to be severe when input voltage are in the below sub threshold levels, which makes the transistor sizing impractical to obtain a proper level shifting [13]. To address this problem, several improvements have been proposed in [13-17]. The LSs in [13-17] are designed and optimized in 130nm technologies to meet the contention issues, can be considered as state of art circuits to convert deep sub threshold to I/O levels. In this brief, for minimization of current contention to attain both efficient and robust level shifting, we introduced new LS with NMOS current limiter which minimizes the dynamic power and propagation delay. Implementation of the LS in 130nm technology makes the