Hindawi Publishing Corporation Active and Passive Electronic Components Volume 2013, Article ID 801634, 10 pages http://dx.doi.org/10.1155/2013/801634 Research Article Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs A. Karsenty 1 and A. Chelly 2 1 Faculty of Engineering, Jerusalem College of Technology, 91160 Jerusalem, Israel 2 Faculty of Engineering, Bar-Ilan University, 52900 Ramat Gan, Israel Correspondence should be addressed to A. Karsenty; karsenty@jct.ac.il Received 20 December 2012; Revised 8 May 2013; Accepted 8 May 2013 Academic Editor: Gerard Ghibaudo Copyright © 2013 A. Karsenty and A. Chelly. Tis is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and lower than 5nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Teir current-voltage characteristics measured at room temperature were found to be surprisingly diferent by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the infuence of a huge series resistance and found that the last one seems more coherent. Ten the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the infuence of the channel thickness on the series resistance is reported for the frst time. Tis infuence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. Tis modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern. 1. Introduction Nanoscale silicon-on-insulator (SOI) metal-oxide-semicon- ductor feld-efect transistor (MOSFET) based devices are the building blocks of up-to-date systems allowing ultrafast data processing. Tis is in accordance with eforts to develop new generation of ultra-fast computers based on combined elec- tronic and signal processing on one hand [1] and advanced generations of nanoscale devices (NSB) for communication systems [2, 3] on the other hand. In this paper, we report the infuence of the silicon channel thickness on the electrical characteristics of SOI MOSFET NSB, and we present an accurate model permitting to evaluate the series resistance and the saturation current as a function of the thickness or of the gate voltage, when part of the aim is to explain the anomalous transport behavior of the thinner channels having a channel’s thickness as low as 1.6nm and obtained by a selective gate-recessed process [4]. Te excellent control of the short channel efects, achiev- able by means of UTB SOI MOSFET architectures, makes them good candidates for ultimate nanometrics scale. Conse- quently, the transport properties’ study of thin semiconductor flms has attracted considerable attention in the recent years. In this paper, we present the infuence of the NSB’s chan- nel thickness on the series resistance in order to complete the unifed model of the NSB’s electrical characteristics. In addition to last years’ existing knowledge in series resistance, these novel interpretative approach and analytical model can be useful for the prediction of transport phenomena at the nanoscale and the correction of electrical characteristics. 2. Methodology 2.1. SIMOX Preferred Wafer Processing Technology. Several techniques were developed in the past to create silicon-on- insulator (SOI) devices [5–8], since their implementation was found promising [9–11] for ULSI [12], low power [13], military and space [14], and cost reducing [15] applications. Nowa- days, SOI wafers are mainly fabricated using the UNIBOND