19 Copyright 2020 | Philippine Engineering Journal Phil. Eng’g J. 2020; 41(1): 19-32 JF Callanga, et al Abstract — In today’s microelectronic industry, the increasing demand for miniaturization and high function integration poses a big challenge in maintaining the reliability of the package. It was found out that majority of the reliability problems can be attributed to thermal and mechanical loadings during manufacturing and assembling process. Die cracking and die tilting are two of the most common defects originating from this process that affect the reliability of the electronic packages. This study aims to investigate the influence of die tilting to the propensity of crack propagation on the silicon die. In this research, the cooling phase of the die and clip attach reflow of small outline transistor was simulated using a finite element-based software. An initial crack was incorporated in the silicon die model to show the imperfections acquired during manufacturing stage. J-integral (J) parameter of fracture mechanics was employed as a criterion for the behavior of incipient cracks. With the assumption that the die used in this study exhibits linear elastic, isotropic property, the calculated J-integral values were correlated to the energy release rate (G). The simulation results showed that as the tilt angle increases, there is also a significant increase in the value of J-integral. The highest J value was observed on the maximum tilt angle. Moreover, this study presents clear relationship between the die strength and the specified failure factors; crack and tilt. Keywords — Fracture Mechanics, ANSYS, Crack Propagation I. INTRODUCTION In a power electronic system, power transistors are its most critical and integral component. As fundamental building block of modern electronic devices, its range of applications varies from household appliances, telecommunication, automotive, spacecraft power supplies, and virtually every aspect of human life [1]. As the demand for functionality and miniaturization increases, power transistors, such as Small Outline Transistors (SOT), are packaged as discrete yet high power density devices. Consequently, these SOT packages are exposed to harsher environment. They are subjected to higher temperature change and increased mechanical loadings like impact and vibrations. These conditions are often the cause of reliability problems, specifically thermo-mechanical, according to Zhang et al. [2]. Based from the same study, approximately 65% of microelectronic failures are due to or related to thermo-mechanical issues arising from the different stages of manufacturing process. One of the most common thermo-mechanical reliability problems is die crack. During the assembly process, packages are exposed to various temperature range and loading conditions. Knowing that these packages are multilayer and multi material, the response of each layer to the changes in temperature varies. The rate of Analysis of Crack Propagation Under Different Die Tilt Configuration on a Small Outline Transistor Jennifer F. Callanga 1 , Hannah Erika D. Macaspac 1 , Louis Angelo M. Danao 1 , Manolo G. Mena 2 1 Department of Mechanical Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines 2 Department of Mining, Metallurgical, and Materials Engineering, University of the Philippines, Diliman, Quezon City, 1101, Philippines PHILIPPINE ENGINEERING JOURNAL PEJ 2020; Vol. 41, No. 1: 19-32