SPICE modelling of hot-carrier degradation in Si 1–x Ge x S/D and HfSiON based pMOS transistors J. Martin-Martinez a, * , E. Amat a , M.B. Gonzalez b,c , P. Verheyen b , R. Rodríguez a , M. Nafría a , X. Aymerich a , E. Simoen b a Universitat Autònoma de Barcelona, Dept. Enginyeria Electrònica, 08193 Bellaterra, Spain b Imec, Kapeldreef 75, B-3001 Leuven, Belgium c KU Leuven, ESAT Department, Leuven, Belgium article info Article history: Received 4 July 2010 Accepted 16 July 2010 Available online 19 August 2010 abstract Hot-carrier degradation in pMOS transistors with Si 1–x Ge x implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a bet- ter device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels. Ó 2010 Elsevier Ltd. All rights reserved. 1. Introduction The device scaling dictated by the ITRS [1] requires changes in the MOSFET structure. One of the most important is the inclusion of high-k materials as gate dielectric [2], which entails new prob- lems, such as the carrier mobility reduction in the channel [3]. In this sense, the selective deposition of epitaxial Si 1–x Ge x layers in the source/drain areas (SiGe S/D) is an effective technique to strain the silicon channel and to enhance the device mobility in pMOS de- vices [4]. However, the effects of aging mechanisms in SiGe S/D de- vices have been scarcely studied [5], and to our knowledge, none of the reports in this field transfer them to the circuit response. In this work, channel hot-carrier (CHC) degradation [6,7] in de- vices with and without SiGe S/D is compared. A simulation meth- odology to easily translate the degradation effects in MOSFETs to the circuit performance is presented. The methodology is applied to include the hot-carrier degradation effects in the circuit re- sponse of CMOS inverters with SiGe S/D pMOS transistors. 2. Samples and experimental The devices used in this work are pMOS transistors (W/L = 1 lm/0.13 lm nominal values) with HfSiON as gate dielectric and Ni-rich FUSI gate. In situ B doped Si 1–x Ge x (x = 0.15) layers were embedded in source and drain regions using an ASM Epsilon Ò 2000 chemical vapor deposition (CVD) epitaxial reactor, to com- pressively strain the silicon channel and enhance the hole mobility. Si reference devices were also studied for comparison. To provoke the device degradation, a high voltage (V G = V D = À2.4 V) was ap- plied to gate and drain terminals whereas source and bulk were grounded, so that, CHC degradation is expected to be the main wear-out mechanism. The electrical stress was periodically inter- rupted to measure the degraded transistor current–voltage (I–V) characteristics. 3. Results 3.1. CHC degradation effects in devices Symbols in Fig. 1 show the typical I D –V G characteristics mea- sured before the electrical stress in fresh (as-grown) transistors with and without SiGe S/D. As expected, for voltages above the threshold voltage (V T ) the channel current is found to be larger in SiGe S/D devices. This result can be explained by the mechanical stress induced hole mobility enhancement. In addition, these sam- ples show lower current in the sub-threshold region, which indi- cates an improvement in the I ON /I OFF ratio in SiGe S/D devices [4]. To study the CHC degradation effects in the transistor perfor- mance, I D –V G curves were measured when the electrical stress was interrupted. From these curves, the evolution with the stress time (t s ) of the threshold voltage shift (DV T ) and the relative mobil- ity variations (l 0 (t s )/l 0 (t s = 0)) have been evaluated (Fig. 2). The V T has been determined from the gate voltage value that must be ap- plied to obtain I D = |1 lA| with V D = À50 mV. Changes in the mobil- ity have been evaluated from variations in the transconductance peak. As can be observed, due to CHC degradation V T increases and l 0 decreases. It is important to notice that the damage induced 0026-2714/$ - see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2010.07.150 * Corresponding author. E-mail address: Javier.martin.martinez@uab.es (J. Martin-Martinez). Microelectronics Reliability 50 (2010) 1263–1266 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel