Int. J. Innovation and Regional Development, Vol. 6, No. 3, 2015 243 Copyright © 2015 Inderscience Enterprises Ltd. Source and IR-level optimisations in the HercuLeS high-level synthesis tool Nikolaos Kavvadias* Ajax Compilers, Voutieridi 7 Rd, 11525 Athens, Greece Email: nkavvadias@ajaxcompilers.com *Corresponding author Kostas Masselos Department of Informatics and Telecommunications, University of Peloponnese, Terma Karaiskaki, 22100 Tripoli, Greece Email: kmas@uop.gr Abstract: HercuLeS is an extensible high-level synthesis environment for automatically mapping algorithms to hardware. It overcomes limitations of known work: insufficient representations, maintenance difficulties, necessity of code templates, lack of usage paradigms and vendor-dependence. Aspects that are highlighted include automatic IP integration and especially source- and intermediate-level optimising transformations. In this context, we present transformational patterns for loop and if-conversion optimisations. Further, we focus on constant multiplication and division by proposing a suitable scheme for their straightforward and decoupled utilisation in user applications. It is shown that loop optimisations provide benefits of up to 32% in cycle performance, while if-conversion delivers an average improvement of 6.5%. By applying arithmetic optimisations, a 3.3–5.9× speedup over sequential implementations is achieved. It is also shown that HercuLeS is highly competitive to state-of-the-art commercial tools. Keywords: hardware; integrated circuits; field-programmable gate arrays; FPGAs; register transfer level; RTL; high-level synthesis; HLS; optimisation. Reference to this paper should be made as follows: Kavvadias, N. and Kavvadias, K. (2015) ‘Source and IR-level optimisations in the HercuLeS high-level synthesis tool’, Int. J. Innovation and Regional Development, Vol. 6, No. 3, pp.243–266. Biographical notes: Nikolaos Kavvadias received his BSc in Physics and MSc in Electronic Physics from the Aristotle University of Thessaloniki, Greece in 1999 and 2002, respectively. In 2008, he received his PhD in Custom Processor Design Methodologies from the same department. From 2008 to 2012, he was a Lecturer at the Department of Computer Science and Technology of the University of Peloponnese, Greece. Since 2012, he is the co-founding CEO of Ajax Compilers. His research interests include high-level synthesis, application-specific/embedded processors and compilation techniques.