A low-voltage and low-power consumption CMOS image sensor using pulse-width-modulation scheme for biomedical applications Sanshiro Shishido 1 , Keiichiro Kagawa 2 , Takashi Tokuda 1 and Jun Ohta 1 1 Graduate School of Materials Science, Nara Institute of Science and Technology Takayama 8916-5, Ikoma, Nara, 630-0101, Japan. Phone: +81-743-72-6051 E-mail: ohta@ms.naist.jp 2 Osaka University 2-1 Yamadaoka, Suita, Osaka, 565-0871, Japan 1. Introduction Recently, a great deal of attention has been paid on CMOS LSI-based biomedical sensors especially for in vivo sensing and imaging applications [1, 2]. For such implantable devices, low power consumption and low operating voltage are required for the sake of long term in vivo operation with battery or wireless electrical power distribution with limited capacity. We have proposed pulse-width-modulation (PWM) pixel-readout scheme as a powerful solution for the bioimplantable imaging devices with low voltage operation and low-power-consumption and demonstrated fundamental characteristics of a fabricated imager with 128 x 96 pixels [3, 4]. In this work, we describe the architecture of our PWM image sensor in detail to increase the pixel number from 128x96 to 352x288 and discuss some essential issues to improve the sensor performance. 2. Operation Principle of the PWM sensor Fig. 1 shows pixel circuit and a timing diagram of the proposed PWM imaging scheme. In the PWM sensor, a photodiode voltage V PD is compared with a ramp signal. The timing of digital transition of the comparator depends on V PD . Thus, the photodiode voltage was transformed into pulse width. The capacity of a power supply can be reduced since the comparator consumes electrical power only around their threshold voltages. In this scheme, signal-to-noise ratio (SNR) is less affected by the reduction of power supply voltage. The benefit comes from low input-referred jitter noise since the in-pixel comparator has a large gain compared with conventional image sensor using source follower circuit its gain is less than one. Fig. 2 shows the sample of the captured image by the prototype PWM sensor [3]. It is generally considered that PWM scheme is disadvantageous from the viewpoint of a pixel size [4]. To shrink the pixel size, we have adopted a 3 transistor/pixel configuration including a one-transistor in-pixel comparator M AMP , as shown in Fig.1. The in-pixel comparator M AMP is always biased during readout period, and the bias current is a main factor of pixel power consumption. We have also proposed and demonstrated a low-power pixel with our PWM sensor based on dynamic operation of in-pixel comparators, and successfully reduced the power consumption in pixel array [5]. 3. Design of the PWM sensor We have designed a PWM sensor with a 0.35μm 2-poly, 3-metals standard CMOS technology. Fig. 3 shows a photograph of the fabricated sensor. The specifications of the PWM sensor chip are summarized in table I. In this design, some improvements were implemented from the prototype sensor [3]. First, we have increased the pixel number from 128×96 to 352×288 which corresponds to Common Intermediate Format (CIF) size. The power-supply voltage was reduced from 1.4V for prototype sensor to 1.2V for the present sensor with an aim of operation with a button-battery. Second, we have lowered the resistance of the ramp signal line to suppress the effect of the IR drop. The horizontal ramp signal line has a finite resistance. Since, all the bias currents for the pixels in a same row are gathered into the ramp signal line, the ramp signal voltage depends on the horizontal pixel position due to IR drop (Fig. 4). To avoid this readout error of the pixel value, we have to take care of an IR drop at the horizontal ramp signal line while readout period. The error of the ramp signal by ΔV ramp,IRdrop is denoted as follows. When all the in-pixel comparators are on, the maximum ΔV ramp,IRdrop appears at the farthest pixel. It is expressed by 2 ) 1 ( max , , + = Δ X X b PIX IRdrop ramp N N I R V . (1) Note that R PIX , I b , and N X are resistance of the ramp signal line for each pixel, bias current for the in-pixel comparator, and the number of the horizontal pixels. Here, I b is denoted by α ) ( min , ramp DD sig Y r b V V C N f I − = . (2) Where f r , N Y , C sig are frame rate, number of vertical pixels, and parasitic capacitance of the vertical signal line. We assume that the ADC period is equal to the one-horizontal period. α means the rate of the transition period of the comparator. It is denoted by V ramp ramp DD A V V V Δ − = min , α . (3) To suppress the error smaller than 1/2 LSB, we have to lower the wiring resistance of ramp signal line in the layout. The maximum acceptable resistance of R PIX is expressed by equation (4). In this work, the ramp signal line consists of parallel-configured metal 1, 2, 3 layers to lower the resistance. ADC N V sig Y r X X PIX A C N f N N R 2 ) 1 ( 1 ⋅ ⋅ ⋅ ⋅ ⋅ + < . (4) Third, we have improved the bootstrap circuit to suppress the variation of the reset level. The prototype sensor had a bootstrap Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -644- P-11-3 pp. 644-645