Analog Integrated Circuits and Signal Processing, 36, 267–272, 2003 c  2003 Kluwer Academic Publishers. Manufactured in The Netherlands. A High Speed, Low Voltage CMOS Offset Comparator AYMAN A. FAYED 1,2 AND M. ISMAIL 2 1 Texas Instruments Inc., 12500 TI Blvd., MS 8730, Dallas, TX 75243, USA 2 Analog VLSI Laboratory, Department of Electrical Engineering, The Ohio State University, 2015 Neil Ave., Columbus, OH 43210, USA E-mail: aafayed@ti.com; fayed.1@osu.edu; ismail@ee.eng.ohio-state.edu Received May 9, 2002; Accepted July 23, 2002 Abstract. A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0–3.6 V and 1.6–2.0 V supplies and -40 to 125 ◦ C temperature range on a typical 0.5 μm technology. Key Words: low-voltage analog circuits, comparators, analog CMOS circuits 1. Introduction Comparators generally serve as an interface between the analog and the digital domain. An offset compara- tor compares a differential input signal with a prede- termined threshold voltage and gives a digital deci- sion accordingly. Offset comparators are usually used in digital communication systems to differentiate be- tween a valid and an invalid differential signal on the data lines. Universal Serial Bus (USB 2.0) system is an example of those systems where a valid differential signal is a signal that has a differential voltage of at least 125 ± 25 mV. Many techniques have been de- veloped in the literature for implementing both regular and offset comparators [1]. A common technique used to implement offset comparators is shown in Fig. 1(a) [2]. The circuit adds the predetermined threshold volt- age (the offset) by applying a differential offset signal to an extra differential pair identical to the primary input differential pair. The main disadvantage of this tech- nique is that in order for the offset to be accurate, the differential signal providing the offset has to have the same common mode as the input signal. Otherwise, due to the finite output impedance of the current sources, the two differential pairs will have different tail cur- rents and consequently different gains, which will lead to significant error in the added offset. This error will vary widely with process, temperature, and supply volt- age. In order to maintain the same common mode for the offset signal and the input signal, a common mode tracking circuit is needed to extract the common mode of the input signal and then provide the differential off- set signal to the extra differential pair [1]. Common mode tracking circuits are required to be slow in or- der to be insensitive to the differential signaling while storing the DC common mode component of the sig- nal. Consequently, a long time will be needed for the common mode tracking circuit to track any change in the common mode of the signal. In some applications, the offset comparator needs to accurately respond to an input signal within a very short time. For example in USB 2.0, the offset comparator has to respond to a differential signal that changes its common mode from 0 to 200 mV within 2.083 ns, which is one bit period. If the common mode circuit is to be designed to respond to a common mode change within one bit period, then it will be sensitive to the differential signaling change as well. This sensitivity will cause the extracted common mode to vary from one bit to another and consequently causing glitches in the output of the comparator. Another technique for implementing offset com- parators is shown in Fig. 1(b). The offset is added by using resistor networks between the supply and ground at the input of a zero-offset comparator. The added offset is dependent on the supply voltage, which varies typically within 10%. In addition to compromis- ing the precision of the offset voltage, the circuit also compromises the high input impedance nature of the comparator. In this letter, we will propose a technique using composite transistors to implement high speed